[Intel-gfx] [RFC PATCH] agp/intel: Fix cache control for Sandybridge
eric at anholt.net
Fri May 28 11:09:21 PDT 2010
On Thu, 27 May 2010 10:55:10 +0800, Zhenyu Wang <zhenyuw at linux.intel.com> wrote:
> Sandybridge GTT has new cache control bits in PTE, which controls
> graphics page cache in LLC or LLC/MLC. This one trys to setup a
> new gtt driver for Gen6, and using new type mask function for that.
> And this sets cache control to always LLC only by default on Gen6.
> As this gtt memory cache control bits are internal to intel hw,
> so I don't add new flags in agp_backend.h but add them only in
> intel_gtt.c. So drm/i915 stuff needs to know these new flags too.
> Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
Please put shared definitions in a header file instead of having two .c
files define them. intel-agp.h maybe? You might need to move the IS_*,
but they should probably be bitfields in device info like they are in
i915 now, and then the macros could go away.
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