[Intel-gfx] [PATCH] enable BLT acceleate on gen6

[Zou, Nanhai]

>>-----Original Message-----
>>From: Chris Wilson [mailto:chris at chris-wilson.co.uk]
>>Sent: 2010年10月30日 3:14
>>To: Zou, Nanhai; intel-gfx at lists.freedesktop.org
>>Subject: Re: [Intel-gfx] [PATCH] enable BLT acceleate on gen6
>>
>>On Fri, 29 Oct 2010 13:18:32 +0800, Zou Nan hai <nanhai.zou at intel.com> wrote:
>>> uxa:	enable BLT command on gen6,
>>> 	BLT command will goto BLT ring buffer
>>> 	on gen6.
>>
>>Just spotted one little fix required, and a couple of other suggestions
>>(as before). Splitting it up into 3 little patches would be best.
>>
>>> Signed-off-by:Zou Nan hai <nanhai.zou at intel.com>
>>> ---
>>> diff --git a/src/intel.h b/src/intel.h
>>> index b74a061..26f4a18 100644
>>> --- a/src/intel.h
>>> +++ b/src/intel.h
>>> @@ -276,6 +276,10 @@ typedef struct intel_screen_private {
>>>  	unsigned char *MMIOBase;
>>>  	int cpp;
>>>
>>> +#define RENDER_BATCH			0
>>> +#define BLT_BATCH			1
>>#define RENDER_BATCH I915_EXEC_RENDER
>>#define BLT_BATCH I915_EXEC_BLT
>>
>>> +	if (ret == 0) {
>>> +		if (intel->current_batch == RENDER_BATCH)
>>> +			ret = dri_bo_exec(intel->batch_bo, intel->batch_used*4,
>>> +					NULL, 0, 0xffffffff);
>>> +		else
>>> +			ret = drm_intel_bo_mrb_exec(intel->batch_bo,
>>> +					intel->batch_used*4,
>>> +					NULL, 0, 0xffffffff, I915_EXEC_BLT);
>>> +	}
>>if (ret == 0)
>>	ret = drm_intel_bo_mrb_exec(intel->batch_bo,
>>				    intel->batch_used*4,
>>				    NULL, 0, 0xffffffff,
>>				    intel->current_batch);
>>> +#define __BEGIN_BATCH(n,batch_idx)					\
>>>  do {									\
>>>  	if (intel->batch_emitting != 0)					\
>>>  		FatalError("%s: BEGIN_BATCH called without closing "	\
>>>  			   "ADVANCE_BATCH\n", __FUNCTION__);		\
>>>  	assert(!intel->in_batch_atomic);				\
>>> +	if (intel->current_batch != batch_idx)				\
>>> +		intel_batch_submit(scrn, TRUE);				\
>>intel_batch_submit(scrn, FALSE);				\
>>

Shouldn't we have a flush here? 
We are switching from 1 batch to another batch.

Thanks
Zou Nanhai

>>-Chris
>>
>>--
>>Chris Wilson, Intel Open Source Technology Centre