[Intel-gfx] [PATCH 05/10] fix send instruction on Sandybridge

[Xiang, Haihao]

Send doesn't have implied move on Sandybridge, the SFID moves to bits[24,27] which
is used as the destination of the implied move on Prev GEN6.

Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
---
 src/brw_structs.h |    2 +-
 src/disasm.c      |    4 ++--
 src/gram.y        |   20 +++++++++++++-------
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/src/brw_structs.h b/src/brw_structs.h
index 515d2aa..92a398e 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
@@ -1053,7 +1053,7 @@ struct brw_instruction
       GLuint predicate_control:4;	/* 0x000f0000 */
       GLuint predicate_inverse:1;	/* 0x00100000 */
       GLuint execution_size:3;		/* 0x00e00000 */
-      GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */
+      GLuint sfid_destreg__conditionalmod:4; /* sfid - send on GEN6+, destreg - send on Prev GEN6, conditionalmod - others */
       GLuint acc_wr_control:1;          /* 0x10000000 */
       GLuint pad0:1;                    /* 0x20000000 */
       GLuint debug_control:1;		/* 0x40000000 */
diff --git a/src/disasm.c b/src/disasm.c
index 37e8b51..8180149 100644
--- a/src/disasm.c
+++ b/src/disasm.c
@@ -795,7 +795,7 @@ int disasm (FILE *file, struct brw_instruction *inst)
 
     if (inst->header.opcode != BRW_OPCODE_SEND)
 	err |= control (file, "conditional modifier", conditional_modifier,
-			inst->header.destreg__conditionalmod, NULL);
+			inst->header.sfid_destreg__conditionalmod, NULL);
 
     if (inst->header.opcode != BRW_OPCODE_NOP) {
 	string (file, "(");
@@ -804,7 +804,7 @@ int disasm (FILE *file, struct brw_instruction *inst)
     }
 
     if (inst->header.opcode == BRW_OPCODE_SEND)
-	format (file, " %d", inst->header.destreg__conditionalmod);
+	format (file, " %d", inst->header.sfid_destreg__conditionalmod);
 
     if (opcode[inst->header.opcode].ndst > 0) {
 	pad (file, 16);
diff --git a/src/gram.y b/src/gram.y
index fcbbd81..2dab7a2 100644
--- a/src/gram.y
+++ b/src/gram.y
@@ -243,7 +243,7 @@ unaryinstruction:
 		{
 		  bzero(&$$, sizeof($$));
 		  $$.header.opcode = $2;
-		  $$.header.destreg__conditionalmod = $3;
+		  $$.header.sfid_destreg__conditionalmod = $3;
 		  $$.header.saturate = $4;
 		  $$.header.execution_size = $5;
 		  set_instruction_options(&$$, &$8);
@@ -264,7 +264,7 @@ binaryinstruction:
 		{
 		  bzero(&$$, sizeof($$));
 		  $$.header.opcode = $2;
-		  $$.header.destreg__conditionalmod = $3;
+		  $$.header.sfid_destreg__conditionalmod = $3;
 		  $$.header.saturate = $4;
 		  $$.header.execution_size = $5;
 		  set_instruction_options(&$$, &$9);
@@ -287,7 +287,7 @@ binaryaccinstruction:
 		{
 		  bzero(&$$, sizeof($$));
 		  $$.header.opcode = $2;
-		  $$.header.destreg__conditionalmod = $3;
+		  $$.header.sfid_destreg__conditionalmod = $3;
 		  $$.header.saturate = $4;
 		  $$.header.execution_size = $5;
 		  set_instruction_options(&$$, &$9);
@@ -322,7 +322,6 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
 		  bzero(&$$, sizeof($$));
 		  $$.header.opcode = $2;
 		  $$.header.execution_size = $3;
-		  $$.header.destreg__conditionalmod = $4; /* msg reg index */
 		  set_instruction_predicate(&$$, &$1);
 		  if (set_instruction_dest(&$$, &$5) != 0)
 		    YYERROR;
@@ -331,15 +330,22 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
 		  $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE;
 		  $$.bits1.da1.src1_reg_type = BRW_REGISTER_TYPE_D;
 
-		  if (gen_level == 5) {
-                      $$.bits2.send_gen5.sfid = $7.bits2.send_gen5.sfid;
-                      $$.bits2.send_gen5.end_of_thread = $12.bits3.generic_gen5.end_of_thread;
+		  if (gen_level >= 5) {
+                      if (gen_level > 5) {
+                          $$.header.sfid_destreg__conditionalmod = $7.bits2.send_gen5.sfid;
+                      } else {
+                          $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */
+                          $$.bits2.send_gen5.sfid = $7.bits2.send_gen5.sfid;
+                          $$.bits2.send_gen5.end_of_thread = $12.bits3.generic_gen5.end_of_thread;
+                      }
+
                       $$.bits3.generic_gen5 = $7.bits3.generic_gen5;
                       $$.bits3.generic_gen5.msg_length = $9;
                       $$.bits3.generic_gen5.response_length = $11;
                       $$.bits3.generic_gen5.end_of_thread =
                           $12.bits3.generic_gen5.end_of_thread;
 		  } else {
+                      $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */
                       $$.bits3.generic = $7.bits3.generic;
                       $$.bits3.generic.msg_length = $9;
                       $$.bits3.generic.response_length = $11;
-- 
1.7.0.4