[Intel-gfx] FPS performance increase when deliberately spinning the CPU with an unrelated task

[Jesse Barnes]

On Mon, 25 Oct 2010 13:11:24 -0700
Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> On Sat, 23 Oct 2010 13:02:35 +0100
> Peter Clifton <pcjc2 at cam.ac.uk> wrote:
> > I think Keith was thinking that there are some parts of the chipset
> > which are shared between the GPU and CPU (memory controllers?), and the
> > CPU entering a lower frequency state could have a detrimental effect on
> > the graphics throughput.
> > 
> > I know in heavy workloads the CPU is likely to be "a bit" busy, and
> > rendering will not be totally GPU bound, but it would seem like it is
> > eventually necessary to have some hook to bump the CPU frequency (or
> > chipset frequency?) when the GPU would make beneficial use of the extra
> > throughput.
> > 
> > This doesn't make sense if it is banging out 100fps, but for my stuff,
> > the GPU is struggling to make 5fps for some complex circuit boards. I'm
> > trying to address that from a geometry / rendering complexity point of
> > view, but also, I'd love to see my laptop being able to get the best out
> > of its hardware.
> > 
> > Perhaps we need to account for periods when the CPU has tasks idle
> > waiting for GPU operations which would be sped up by increasing some
> > chip power state.
> > 
> > I'm probably not up to coding this all, but if the idea sounds feasible,
> > I'd love to know, so I might be able to have a tinker with it.
> 
> There are some bits in the GMCH to control memory behavior during CPU
> C-states.  Can you dump the 16 bits at MCHBAR address 0xf08?  You
> should be able to do that by doing I915_READ16(MCHBAR_MIRROR_BASE +
> 0xf08).  Assuming bits 3:2 and 1:0 are nonzero, it may help to set them
> all to 0.  That will disable several memory related power saving
> features while the CPU is in a deep sleep state.

Oh and bits 5:4 and bit 6 as well.  Bit 6 controls whether memory stays
active in C2, and bits 5:4 control which memory shutdown features are
enabled in C2; clearing 5:4 will disable shutdown, as will bit 6.

-- 
Jesse Barnes, Intel Open Source Technology Center