[Intel-gfx] [PATCH] drm/i915: Clear any errors recorded before i915.ko is loaded

[Chris Wilson]

This looks like it fixes two bugs:

1) What if there is an error recorded before we start and so we
immediately service an IIR/EIR upon intalling the IRQ. Did we generate
that error during initialisation or was that SEP? Now we do stuff before
we even install the IRQ so there is a possibility that we zap one of our
own.

2) When re-enabling the interrupt (gpu reset) we need to preserve any
masking of stuck EIR.

I guess this is easiest to test by generating an EIR, then reloading the
module? Does EIR even persist between phases to cause these issues in
the first place?

Something to think about...
---
 drivers/gpu/drm/i915/i915_irq.c |   16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 46ccfc8..bb1a624 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1650,11 +1650,24 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static void i915_irq_clear_errors(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 eir = I915_READ(EIR);
+	if (eir) {
+		I915_WRITE(EIR, eir);
+		POSTING_READ(EIR);
+	}
+}
+
 void i915_driver_irq_preinstall(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 
+	/* Clear any errors recorded before we begin. */
+	i915_irq_clear_errors(dev);
+
 	atomic_set(&dev_priv->irq_received, 0);
 
 	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
@@ -1719,7 +1732,8 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
 		error_mask = ~(I915_ERROR_PAGE_TABLE |
 			       I915_ERROR_MEMORY_REFRESH);
 	}
-	I915_WRITE(EMR, error_mask);
+	/* Some pre-existing errors might have become stuck, mask them.  */
+	I915_WRITE(EMR, error_mask | I915_READ(EIR));
 
 	I915_WRITE(IMR, dev_priv->irq_mask);
 	I915_WRITE(IER, enable_mask);
-- 
1.7.4.1