[Intel-gfx] [PATCH] drm/i915: read/write IOCTLs
chris at chris-wilson.co.uk
Mon Apr 4 00:36:57 PDT 2011
On Sun, 3 Apr 2011 18:35:04 -0700, Ben Widawsky <ben at bwidawsk.net> wrote:
> Here is the data from ~100 samples while playing playing Armacycles Advanced
> measured off of d-i-f 7f58aabc369014fda3a4a33604ba0a1b63b941ac.
> min 02.775us
> max 19.402us
> avg 07.057us
> stddev 02.819us
> When I do a cat /sys/kernel/debug/dri/0/i915_gem_interrupt, I always get
> 3 reads, in a similar pattern to this:
> 6) ! 285.852 us | __gen6_gt_force_wake_get();
> 6) 1.944 us | __gen6_gt_force_wake_get();
> 6) 1.854 us | __gen6_gt_force_wake_get();
> Not sure why that case is so different.
Presumably the high cost is when we need to wait for the GT to power up
and the hardware has its own hysteresis and will delay before powering
down again. [It also looks like we always have to wait at least for one
loop. Perhaps a posting read is in order?] So at least we don't have to
worry about doing that ourselves - adding a spinlock just for performance
optimisation on a seldom used debugging ioctl is painful.
Chris Wilson, Intel Open Source Technology Centre
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