[Intel-gfx] [PATCH] drm/i915: Relinquish any fence when changing cache levels

Daniel Vetter daniel at ffwll.ch
Wed Apr 13 22:46:47 CEST 2011

On Wed, Apr 13, 2011 at 07:01:11PM +0100, Chris Wilson wrote:
> This is vital to maintain our contract with the hw for not using fences
> on snooped memory for older chipsets. It should have no impact
> other than clearing the fence register (and updating the fence
> bookkeeping) as any future IO access (page faults or pwrite/pread) will
> be linear and go through the cached CPU domain.

set_cache_level is rather unused on pre-snb. Can't we just hold off with
such complexity before we actually use it in e.g. the vmap code? Maybe add
a WARN_ON(gen < 6) instead?

Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48

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