[Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)

[Eric Anholt]

On Wed, 7 Dec 2011 13:03:29 -0800, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> On Wed, 07 Dec 2011 12:54:07 -0800
> Eric Anholt <eric at anholt.net> wrote:
> 
> > On Wed, 7 Dec 2011 11:58:05 -0800, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> > > On Wed, 7 Dec 2011 10:38:41 -0800
> > > Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> > > 
> > > > On Wed, 07 Dec 2011 10:35:45 -0800
> > > > Eric Anholt <eric at anholt.net> wrote:
> > > > 
> > > > > On Sat, 22 Oct 2011 19:41:24 -0700, Ben Widawsky <ben at bwidawsk.net> wrote:
> > > > > > The docs say this is required for Gen7, and since the bit was added for
> > > > > > Gen6, we are also setting it there pit pf paranoia. Particularly as
> > > > > > Chris points out, if PIPE_CONTROL counts as a 3d state packet.
> > > > > > 
> > > > > > This was found through doc inspection by Ken and applies to Gen6+;
> > > > > > 
> > > > > > Cc: Keith Packard <keithp at keithp.com>
> > > > > > Reported-by: Kenneth Graunke <kenneth at whitecape.org>
> > > > > > Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> > > > > > Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
> > > > > > Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> > > > > 
> > > > > Reviewed-by: Eric Anholt <eric at anholt.net>
> > > > > 
> > > > > however, it doesn't appear to help Ivybridge IRQ troubles.
> > > > 
> > > > You could try something like the below to force the use of PIPE_NOTIFY
> > > > instead.  Only lightly tested on IVB when we had lots of other bugs, so
> > > > I'm not sure if it works at all.
> > > 
> > > Though if it's the blit ring hanging, you'd have to try using a
> > > flush_dw notify (if such a thing exists) instead...
> > 
> > Yeah, MI_FLUSH_DW as opposed to MI_STORE_DW + MI_USER_INTERRUPT.
> 
> Looks like there is a notify option, bit 8 of MI_FLUSH_DW.  It's a long
> shot, but does anyone want to give it a try?

Since MI_FLUSH_DW exists on gen6, and keithp says we still have
outstanding issues with missed blit IRQs there, I started trying it
today.  Two kernel branches posted at
git://people.freedesktop.org/~anholt/linux/

flush-dw-notify: This is the initial attempt I did with MI_FLUSH_DW with
internal notify.  Quickly produced missed blit IRQs.  I thought this was
because the notify was in parallel with the post-sync op, not synced to
be after.  So I reverted part of the patch and produced...

flush-dw: This branch still uses MI_USER_INTERRUPT, with a commit message
explaining my theory as to why it works while the previous attempt
didn't.  But if my theory is correct, then the head commit of that
(removing the HWSTAM update of HWS at interrupt time) should be safe,
while that commit pretty quickly produced missed interrupts.

So, while I've got code at flush-dw~1 that appears to work equivalently
to master, my mental model of how the hardware works is clearly still
not correct.

On gen7, flush-dw~1 still misses IRQs.  flush-dw-notify still misses
irqs as well, but it may make them less frequent.  It would take more
testing to quantify.

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