[Intel-gfx] [PATCH] drm/i915: set cache sharing policy to max sharing on SNB+

[Jesse Barnes]

By default, the GPU will only share a very small portion of the CPU
cache.  With this change, both the GPU and CPU will have full access to
the cache, which should help (sometimes a lot) in most cases.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |    5 +++++
 drivers/gpu/drm/i915/intel_display.c |    7 +++++++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a446b1..eac59f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -78,6 +78,11 @@
 #define  GRDOM_RENDER	(1<<2)
 #define  GRDOM_MEDIA	(3<<2)
 
+#define GEN6_MBCUNIT_CFG	0x900c /* for LLC config */
+#define   GEN6_MBC_LLC_CFG_MASK	(3<<21)
+#define   GEN6_MBC_LLC_CFG_FULL	(1<<21) /* full sharing of 16/16ths of the cache */
+#define   GEN6_MBC_LLC_CFG_MIN	(3<<21) /* only 1/16th of the cache is shared */
+
 #define GEN6_GDRST	0x941c
 #define  GEN6_GRDOM_FULL		(1 << 0)
 #define  GEN6_GRDOM_RENDER		(1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 823b8d9..0ed4ed2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7279,6 +7279,7 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 	int min_freq = 15;
 	int gpu_freq, ia_freq, max_ia_freq;
 	int scaling_factor = 180;
+	u32 mbccfg;
 
 	max_ia_freq = cpufreq_quick_get_max(0);
 	/*
@@ -7293,6 +7294,12 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->dev->struct_mutex);
 
+	/* Update the cache sharing policy here as well */
+	mbccfg = I915_READ(GEN6_MBCUNIT_CFG);
+	mbccfg &= ~GEN6_MBC_LLC_CFG_MASK;
+	mbccfg |= GEN6_MBC_LLC_CFG_FULL;
+	I915_WRITE(GEN6_MBCUNIT_CFG, mbccfg);
+
 	/*
 	 * For each potential GPU frequency, load a ring frequency we'd like
 	 * to use for memory access.  We do this by specifying the IA frequency
-- 
1.7.4.1