[Intel-gfx] [PATCH] drm/i915: apply phase pointer override on SNB+ too

[Jesse Barnes]

These bits moved around on SNB and above.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |   12 ++++++++++++
 drivers/gpu/drm/i915/intel_display.c |   34 ++++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..d5a9812 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3075,6 +3075,18 @@
 #define  TRANS_6BPC             (2<<5)
 #define  TRANS_12BPC            (3<<5)
 
+#define _TRANSA_CHICKEN2	 0xf0064
+#define _TRANSB_CHICKEN2	 0xf1064
+#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define   TRANS_AUTOTRAIN_GEN_STALL_DIS	(1<<31)
+
+#define SOUTH_CHICKEN1		0xc2000
+#define  FDIA_PHASE_SYNC_OVR	(1<<19)
+#define  FDIA_PHASE_SYNC_EN	(1<<18)
+#define  FDIB_PHASE_SYNC_OVR	(1<<17)
+#define  FDIB_PHASE_SYNC_EN	(1<<16)
+#define  FDIC_PHASE_SYNC_OVR	(1<<15)
+#define  FDIC_PHASE_SYNC_EN	(1<<14)
 #define SOUTH_CHICKEN2		0xc2004
 #define  DPLS_EDP_PPS_FIX_DIS	(1<<0)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5609c06..187b035 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2133,6 +2133,23 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
 			   FDI_RX_PHASE_SYNC_POINTER_EN);
+	} else if (HAS_PCH_CPT(dev)) {
+		u32 flags;
+		switch (pipe) {
+		case 0:
+			flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+			break;
+		case 2:
+			flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+			break;
+		case 3:
+			flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+			break;
+		default:
+			break;
+		}
+		I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+		I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
 	}
 
 	reg = FDI_RX_IIR(pipe);
@@ -2490,6 +2507,23 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
 		I915_WRITE(FDI_RX_CHICKEN(pipe),
 			   I915_READ(FDI_RX_CHICKEN(pipe) &
 				     ~FDI_RX_PHASE_SYNC_POINTER_EN));
+	} else if (HAS_PCH_CPT(dev)) {
+		u32 flags;
+		switch (pipe) {
+		case 0:
+			flags = FDIA_PHASE_SYNC_OVR;
+			break;
+		case 2:
+			flags = FDIA_PHASE_SYNC_OVR;
+			break;
+		case 3:
+			flags = FDIA_PHASE_SYNC_OVR;
+			break;
+		default:
+			break;
+		}
+		I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+		I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
 	}
 
 	/* still set train pattern 1 */
-- 
1.7.4.1