[Intel-gfx] [PATCH] drm/i915: Reset GMBUS controller after NAK
keithp at keithp.com
Wed Mar 30 10:22:48 PDT 2011
On Wed, 30 Mar 2011 17:59:51 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> I'm not even sure we need the first posting read. Maybe it should be a
> wait_for(I915_READ(GMBUS1 + reg_offset) & GMBUS_SW_CLR_INT, 100)
> to be clearer that we are simply giving the hardware the chance to assert
> the bit and reset before re-enabling.
Doesn't look like the hardware actually delays in setting this bit, so
your original sequence should be correct. Of course, a comment
indicating that you're toggling the SW_CLR_INT bit to reset the bus
might be nice.
> No, GMBUS0 is not read until the very first phase of the data cycle. And
> the very first thing we do in the next xfer is a write to GMBUS0 of the
> port settings. I just thought that explicitly marking the GMBUS controller
> as disabled when not in use by us would lead to less confusion in
Sounds reasonable. I'd love to have seen a comment in the code and in
keith.packard at intel.com
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