[Intel-gfx] [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level
eric at anholt.net
Thu Mar 31 13:10:22 PDT 2011
On Thu, 31 Mar 2011 08:29:31 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> On Wed, 30 Mar 2011 14:45:11 -0700, Eric Anholt <eric at anholt.net> wrote:
> > On Wed, 30 Mar 2011 18:16:11 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> > > On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt <eric at anholt.net> wrote:
> > > > And what about a CPU write through the GTT?
> > >
> > > Even on SNB these are still UC. And we should try hard not to, as the
> > > specs give dire warnings about writing to snooped PTEs through the GTT.
> > > (Since we will bypass the caches with the write, aiui, and cause
> > > confusion.)
> > Oh, wow. That's really bad. Reject this series if so.
> I plucked that tidbit out of the specs for the BLT engine, which has not
> been rigorously updated since gen2... Though don't we also encounter a few
> subtleties with movnta (__copy_from_user_nocache_nozero from pwrite) and
> data in cachelines?
The only tricky correctness bit for those was how to flush the little
tiny movnt cache when you're done, which is "mfence". As far as other
interesting notes about movnt, it doesn't mean that the destination is
not in cache after the instruction -- if it was already in cache, it
will likely be in cache afterwards. I don't think that has any impact
on how we do our code.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Size: 197 bytes
Desc: not available
More information about the Intel-gfx