[Intel-gfx] [PATCH 12/16] drm/915: fix relaxed tiling on gen2: tile height
daniel at ffwll.ch
Sun May 15 13:43:41 PDT 2011
On Thu, May 12, 2011 at 06:13:32PM -0700, Keith Packard wrote:
> On Thu, 12 May 2011 22:17:20 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> > From: Daniel Vetter <daniel.vetter at ffwll.ch>
> > A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.
> > Userspace was broken and assumed 8 rows. Chris Wilson noted that the
> > kernel unfortunately can't reliable check that because libdrm rounds
> > up the size to the next bucket.
> Please explain (in the commit message) the impact on both new and old
> user space. I remember (vaguely) that this patch will cause old user
> space to have issues.
No problem for old userspace. This only changes the number of rows from 32
to 16. This value is used in the kernel to align buffers correctly, i.e.
it will save perhaps a tiny bit of gtt. Userspace on the other hand
assumed only 8 rows, which lead to underallocating it the last tile row.
So this patch is more documentation of actual hw behaviour than anything
else - hopefully getting rid of gen2 tiling confusion once and for all.
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
More information about the Intel-gfx