[Intel-gfx] [PATCH 12/16] drm/915: fix relaxed tiling on gen2: tile height
keithp at keithp.com
Sun May 15 14:58:26 PDT 2011
On Sun, 15 May 2011 22:43:41 +0200, Daniel Vetter <daniel at ffwll.ch> wrote:
> No problem for old userspace. This only changes the number of rows from 32
> to 16. This value is used in the kernel to align buffers correctly, i.e.
> it will save perhaps a tiny bit of gtt. Userspace on the other hand
> assumed only 8 rows, which lead to underallocating it the last tile
I have this vague memory of some problem in the past with tiling and old
user space for Gen2 hardware. I assume that old user space will just do
bad things, but that there's nothing the kernel can do to fix it, right?
The requirement here is that kernel changes not break user space, even
if the kernel was just masking a user-space bug. If that isn't true for
any old user space version, then this should be fine.
> So this patch is more documentation of actual hw behaviour than anything
> else - hopefully getting rid of gen2 tiling confusion once and for all.
Cool. Thanks for the clarification.
keith.packard at intel.com
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