[Intel-gfx] Is MI_FLUSH_ENABLE bit 12?
ben at bwidawsk.net
Wed Nov 30 04:42:00 CET 2011
On Tue, Nov 29, 2011 at 04:47:57PM -0800, Eric Anholt wrote:
> On Mon, 28 Nov 2011 18:48:04 -0800, "Keith Packard" <keithp at keithp.com> wrote:
> Non-text part: multipart/mixed
> Non-text part: multipart/signed
> > Just reading through vol1c.4 of the bspec this evening and found something odd.
> > Bit 11 of MI_MODE is "Invalidate UHPTR enable".
> > Bit 12 of MI_MODE is "MI_FLUSH Enable"
> > And, yet, in i915_reg.h:
> > #define MI_MODE 0x0209c
> > # define VS_TIMER_DISPATCH (1 << 6)
> > # define MI_FLUSH_ENABLE (1 << 11)
> > Are we off-by-one on MI_FLUSH_ENABLE? Seems like this would cause
> > serious problems...
> I think we are. On the other hand, based on actual behavior plus
> reading of simulator, I believe that the bit does nothing, regardless.
I do not think so. We've (Chris, I, and perhaps Jesse?) been through
this excercise at least twice before, and both times resulted in hangs
when we switched to bit 12 on Ironlake, not sure about other platforms.
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