[Intel-gfx] [PATCH 4/4] drm/i915: more 3 pipe support

[Eugeni Dodonov]

On Wed, Oct 5, 2011 at 16:48, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> On Wed,  5 Oct 2011 10:25:21 -0700
> Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
>
> > Handle PLL allocation and transcoder select bits on CPT+.
>
> Updated patch that fixes the bug with VGA plus two HDMI.  Was missing
> the composite sync bits in the FDI TX side (setting them everywhere
> here just to be safe).
>
> --
> Jesse Barnes, Intel Open Source Technology Center
>


The following chunk which we discussed on IRC earlier today made it work
correctly on IVB:

>From 8a5e2eb86f62ab14ca0c12b16628e009d1fcbe98 Mon Sep 17 00:00:00 2001
From: Eugeni Dodonov <eugeni.dodonov at intel.com>
Date: Wed, 5 Oct 2011 18:34:09 -0300
Subject: [PATCH] Enable composite sync bit on IVB

Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e63a187..26cadff 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2608,6 +2608,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc)
     temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
     temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
     temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+    temp |= FDI_COMPOSITE_SYNC;
     I915_WRITE(reg, temp | FDI_TX_ENABLE);

     reg = FDI_RX_CTL(pipe);
@@ -2615,6 +2616,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc)
     temp &= ~FDI_LINK_TRAIN_AUTO;
     temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
     temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+    temp |= FDI_COMPOSITE_SYNC;
     I915_WRITE(reg, temp | FDI_RX_ENABLE);

     POSTING_READ(reg);
-- 
1.7.6.4

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>
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