[PATCH] Enable composite sync bit on IVB

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e63a187..26cadff 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2608,6 +2608,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc)
     temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
     temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
     temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+    temp |= FDI_COMPOSITE_SYNC;
     I915_WRITE(reg, temp | FDI_TX_ENABLE);

     reg = FDI_RX_CTL(pipe);
@@ -2615,6 +2616,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc)
     temp &= ~FDI_LINK_TRAIN_AUTO;
     temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
     temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+    temp |= FDI_COMPOSITE_SYNC;
     I915_WRITE(reg, temp | FDI_RX_ENABLE);

     POSTING_READ(reg);
-- 
1.7.6.4

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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<div class=3D"gmail_quote">On Wed, Oct 5, 2011 at 16:48, Jesse Barnes <span=
 dir=3D"ltr">&lt;<a href=3D"mailto:jbarnes at virtuousgeek.org">jbarnes at virtuo=
usgeek.org</a>&gt;</span> wrote:<br><blockquote class=3D"gmail_quote" style=
=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">

<div class=3D"im">On Wed, =A05 Oct 2011 10:25:21 -0700<br>
Jesse Barnes &lt;<a href=3D"mailto:jbarnes at virtuousgeek.org">jbarnes at virtuo=
usgeek.org</a>&gt; wrote:<br>
<br>
&gt; Handle PLL allocation and transcoder select bits on CPT+.<br>
<br>
</div>Updated patch that fixes the bug with VGA plus two HDMI. =A0Was missi=
ng<br>
the composite sync bits in the FDI TX side (setting them everywhere<br>
here just to be safe).<br>
<br>
--<br>
Jesse Barnes, Intel Open Source Technology Center<br></blockquote><div><br>=
<br>
The following chunk which we discussed on IRC earlier today made it work co=
rrectly on IVB:<br>

<br clear=3D"all"></div></div>From 8a5e2eb86f62ab14ca0c12b16628e009d1fcbe98=
 Mon Sep 17 00:00:00 2001<br>From: Eugeni Dodonov &lt;<a href=3D"mailto:eug=
eni.dodonov at intel.com">eugeni.dodonov at intel.com</a>&gt;<br>Date: Wed, 5 Oct=
 2011 18:34:09 -0300<br>

Subject: [PATCH] Enable composite sync bit on IVB<br><br>Signed-off-by: Eug=
eni Dodonov &lt;<a href=3D"mailto:eugeni.dodonov at intel.com">eugeni.dodonov@=
intel.com</a>&gt;<br>---<br>=A0drivers/gpu/drm/i915/intel_display.c |=A0=A0=
=A0 2 ++<br>

=A01 files changed, 2 insertions(+), 0 deletions(-)<br><br>diff --git a/dri=
vers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c<br=
>index e63a187..26cadff 100644<br>--- a/drivers/gpu/drm/i915/intel_display.=
c<br>

+++ b/drivers/gpu/drm/i915/intel_display.c<br>@@ -2608,6 +2608,7 @@ static =
void ivb_manual_fdi_link_train(struct drm_crtc *crtc)<br>=A0=A0=A0=A0 temp =
|=3D FDI_LINK_TRAIN_PATTERN_1_IVB;<br>=A0=A0=A0=A0 temp &amp;=3D ~FDI_LINK_=
TRAIN_VOL_EMP_MASK;<br>

=A0=A0=A0=A0 temp |=3D FDI_LINK_TRAIN_400MV_0DB_SNB_B;<br>+=A0=A0=A0 temp |=
=3D FDI_COMPOSITE_SYNC;<br>=A0=A0=A0=A0 I915_WRITE(reg, temp | FDI_TX_ENABL=
E);<br>=A0<br>=A0=A0=A0=A0 reg =3D FDI_RX_CTL(pipe);<br>@@ -2615,6 +2616,7 =
@@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)<br>

=A0=A0=A0=A0 temp &amp;=3D ~FDI_LINK_TRAIN_AUTO;<br>=A0=A0=A0=A0 temp &amp;=
=3D ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;<br>=A0=A0=A0=A0 temp |=3D FDI_LINK_TR=
AIN_PATTERN_1_CPT;<br>+=A0=A0=A0 temp |=3D FDI_COMPOSITE_SYNC;<br>=A0=A0=A0=
=A0 I915_WRITE(reg, temp | FDI_RX_ENABLE);<br>

=A0<br>=A0=A0=A0=A0 POSTING_READ(reg);<br>-- <br>1.7.6.4<br><br>-- <br>Euge=
ni Dodonov<a href=3D"http://eugeni.dodonov.net/" target=3D"_blank"><br></a>=
<br>

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