[Intel-gfx] [PATCH 3/5] drm/i915/pch: Fix thinko in DPLL disable

[Jesse Barnes]

On Fri,  7 Oct 2011 14:38:44 -0400
Adam Jackson <ajax at redhat.com> wrote:

> For transcoder A, we would never clear the DPLL[AB] select bit.  If the
> firmware had set us up on DPLLB, the effect would be to attempt to use
> DPLLB for both pipes A and B, which would probably be bad.
> 
> Signed-off-by: Adam Jackson <ajax at redhat.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9edf363..67dbe22 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3051,7 +3051,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  		temp = I915_READ(PCH_DPLL_SEL);
>  		switch (pipe) {
>  		case 0:
> -			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
> +			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
>  			break;
>  		case 1:
>  			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);

I think this might be even better (goes with the 3 pipe patches)?

-- 
Jesse Barnes, Intel Open Source Technology Center

From 159f6191ed19c0d39f986c1bcbd4652d40525108 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes at virtuousgeek.org>
Date: Wed, 12 Oct 2011 15:01:33 -0700
Subject: [PATCH] drm/i915: fix transcoder PLL select masking

Transcoder A will always use PLL A and transcoder B will use PLL B.  But
transcoder C could use either, so always mask the select bits off before
or'ing in a new value.

Reported-by: Adam Jackson <ajax at redhat.com>
Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 91f0855..77fc268 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2902,8 +2902,10 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 			temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
 		else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
 			temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
-		else if (pipe == 2 && (temp & TRANSC_DPLL_ENABLE) == 0)
+		else if (pipe == 2 && (temp & TRANSC_DPLL_ENABLE) == 0) {
+			temp &= ~(TRANSC_DPLLB_SEL);
 			temp |= (TRANSC_DPLL_ENABLE | transc_sel);
+		}
 		I915_WRITE(PCH_DPLL_SEL, temp);
 	}
 
@@ -3069,10 +3071,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 		temp = I915_READ(PCH_DPLL_SEL);
 		switch (pipe) {
 		case 0:
-			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
+			temp &= ~TRANSA_DPLL_ENABLE;
 			break;
 		case 1:
-			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
+			temp &= ~TRANSB_DPLL_ENABLE;
 			break;
 		case 2:
 			/* C shares PLL A or B */
@@ -5540,6 +5542,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 			temp |=	TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
 			break;
 		case 2:
+			temp &= ~(TRANSC_DPLLB_SEL);
 			temp |= TRANSC_DPLL_ENABLE | transc_sel;
 			break;
 		default:
-- 
1.7.4.1


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