[Intel-gfx] [PATCH 5/5] drm/i915: Force sync command ordering (Gen6+)
ben at bwidawsk.net
Wed Oct 12 01:01:43 PDT 2011
On Oct 11, 2011, at 9:43 PM, Ben Widawsky <ben at bwidawsk.net> wrote:
> The docs say this is required for Gen7, and since the bit was added for
> Gen6, we are also setting it there pit pf paranoia. Particularly as
> Chris points out, if PIPE_CONTROL counts as a 3d state packet.
> This was found through doc inspection by Ken and applies to Gen6+;
> It is currently hanging Daniel's maching.
> Reported-by: Kenneth Graunke <kenneth at whitecape.org>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+), 0 deletions(-)
It appears I dropped the second hunk by mistake.
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