[Intel-gfx] [PATCH 1/3] drm/i915: Ivybridge still has fences!
daniel at ffwll.ch
Mon Oct 24 00:16:56 CEST 2011
On Sun, Oct 23, 2011 at 01:45:21PM -0700, Kenneth Graunke wrote:
> On 10/23/2011 04:23 AM, Chris Wilson wrote:
> > Regardless of the outcome of Jesse's request for an if-ladder, the
> > substance of the patches look sound.
> > However, I remain unconvinced that there are 32 fence registers on IVB.
> > Daniel's evidence is based upon the size of the register map (and not
> > on the BSPEC explicitly stating a change to 32 ;-), but most tellingly
> > the bitfields for fence-number in other registers have not been updated -
> > so we can only safely allocated the first 16 anyway...
> > (For instance, FBC_CTL).
> > -Chris
> It sure looks like it has 32 fence registers: BSpec vol1g GT Interface
> Register [DevIVB] / GT Interface Register DevIVB / System Agent Config
> Space lists FENCE0 through FENCE31. The simulator seems to indicate
> this as well.
> You're right that FBC_CTL still only has 4 bits for selecting a fence,
> but notably, in the latest (WIP) version of the BSpec, it says "This
> field must be programmed to 0000b." I'm not sure how it's supposed to
> work now, but likely something has changed.
See my other mail. The cpu fence is specified in DPCF_CONTROL_SA, which
has again 4 bits on snb, but enough free room for 5 bits. Now on some
future hw I'm not allowed to talk about, these 5 bits exist (see
MPGFXTRK_CR_DPFC_CONTROL_SA_0_2_0_GTTMMADR in bspec), but unfortunately
not on ivb. So if you could hunt around in the sim code and check whether
that is already implemented on ivb, that'd be awesome.
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
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