[Intel-gfx] [PATCH] drm/i915: Use PIPE_CONTROL for flushing on gen6+.
ben at bwidawsk.net
Sun Oct 16 18:27:55 PDT 2011
On Sun, 16 Oct 2011 10:23:31 +0200
Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> From: Jesse Barnes <jbarnes at virtuousgeek.org>
> v2 by danvet: Use a new flag to flush the render target cache on gen6+
> (hw reuses the old write flush bit), as suggested by Ben Widawsdy.
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> [danvet: this seems to fix cairo-perf-trace hangs on my snb]
> Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
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