[Intel-gfx] [PATCH 1/3] drm/i915: Ivybridge still has fences!
daniel at ffwll.ch
Sun Oct 23 05:09:07 PDT 2011
On Sun, Oct 23, 2011 at 12:23:14PM +0100, Chris Wilson wrote:
> Regardless of the outcome of Jesse's request for an if-ladder, the
> substance of the patches look sound.
> However, I remain unconvinced that there are 32 fence registers on IVB.
> Daniel's evidence is based upon the size of the register map (and not
> on the BSPEC explicitly stating a change to 32 ;-), but most tellingly
> the bitfields for fence-number in other registers have not been updated -
> so we can only safely allocated the first 16 anyway...
> (For instance, FBC_CTL).
Ok, I've rechecked bspec. The FBC_CTL fence number is indeed only 4 bits
wide, but on snb+ is must be written as 0. The cpu fence stuff for fbc
moved to DPFC_CONTROL_SA, which has room enough for 5 bits. Unfortunately
bspec is silent on whether that has actually grown from 4 bits for ivb. On
a future hw iteration I'm not really allowed to talk about it is all
correctly in place (i.e. bspec definitions for all 32 fence regs plus the
5 bit wide fence number in DPFC_CTL_SA).
So I think I'll drop this patch till things clear up.
Keith, can take a look at patches 1-2 and consider merging them for 3.2?
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
More information about the Intel-gfx