[Intel-gfx] [PATCH] [RFC] drm/i915: Unmask all render responses for SNB

[Chris Wilson]

On SandyBridge in order to receive an event on the RENDER ring, you
first must unmask the corresponding bit in the DERRMR (Display Engine
Render Response Mask Register). This register is not accessible from a
non-secure MI_LOAD_REGISTER_IMM so resort to unmasking all events upon
initialisation. Presumably this leads to an undesirable increase in PCI
traffic (possibly 4 additional wakeups per vblank per active pipe).

More tricky solutions include extending EXECBUFFER to include a request
to enable the appropriate render response and for the kernel to unmask
and reset around the batch. Also we need to include a flag to indicate
that it is safe to use MI_WAIT_FOR_EVENT as well.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_reg.h      |   11 +++++++++++
 drivers/gpu/drm/i915/intel_display.c |    3 +++
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b8b796f..29c4aaa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2661,6 +2661,17 @@
 #define  DIGITAL_PORTA_LONG_PULSE_DETECT_MASK   (1 << 1)
 #define  DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK  (1 << 0)
 
+/* Display Engine Render Response Mask Register */
+#define GEN6_DERRMR      0x44050
+#define   DER_PIPE_A_SCANLINE_EVENT		(1 << 0)
+#define   DER_PIPE_A_PRIMARY_FLIP_DONE		(1 << 1)
+#define   DER_PIPE_A_SPRITE_FLIP_DONE		(1 << 2)
+#define   DER_PIPE_A_VBLANK_START		(1 << 3)
+#define   DER_PIPE_B_SCANLINE_EVENT		(1 << 8)
+#define   DER_PIPE_B_PRIMARY_FLIP_DONE		(1 << 9)
+#define   DER_PIPE_B_SPRITE_FLIP_DONE		(1 << 10)
+#define   DER_PIPE_B_VBLANK_START		(1 << 11)
+
 /* refresh rate hardware control */
 #define RR_HW_CTL       0x45300
 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 756dddc..dfe14ac 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7888,6 +7888,9 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 			   DISPPLANE_TRICKLE_FEED_DISABLE);
 		intel_flush_display_plane(dev_priv, pipe);
 	}
+
+	/* Unmask all render responses so that MI_WAIT_FOR_EVENT just works */
+	I915_WRITE(GEN6_DERRMR, 0);
 }
 
 static void ivybridge_init_clock_gating(struct drm_device *dev)
-- 
1.7.6.3