[Intel-gfx] PCH reference clock cleanups

Keith Packard keithp at keithp.com
Tue Sep 27 08:11:37 CEST 2011

Here's a patch sequence which cleans up a bunch of PCH refclk related
bits. There are a couple of questionable patches that I'd like to see
people look at:

 [PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings
 [PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time

Here's the main patch -- this looks at the global set of encoders and
figures out what the refclk should be to make all of those work
correctly. Nothing is dependent on the active configuration, so we
aren't reprogramming this register during run-time. The last patch in
the sequence moves the setting of this register from modeset time to
init time.

 [PATCH 7/9] drm/i915: Use CK505 as non-SSC source where available

This is a small piece straight from Jesse's patch; just uses the VBT
configuration for CK505 clock sources.

 [PATCH 8/9] drm/i915: All PCH refclks are 120MHz

Ok, so I'd love to know where in any PCH reference matter someone has
found a place where the reference clock for any of the PLLs is
anything other than 120MHz. Can someone find a reference for other frequencies?

keith.packard at intel.com

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