[Intel-gfx] [PATCH] Mask reserved bits in display/sprite address registers
daniel at ffwll.ch
Mon Apr 9 13:11:44 PDT 2012
On Mon, Apr 09, 2012 at 03:48:03PM +0000, Reese, Armin C wrote:
> Thanks for the review, Ben.
> Yes, I was a bit paranoid about what values could be in gtt_offset. But
> if it's always a multiple of 0x1000, we can save an additional mask
> operation. I'll make the change and resubmit.
And a small style nitpick: Please prepend "drm/i915: " to your patch
headline when resending.
Mail: daniel at ffwll.ch
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