[Intel-gfx] [PATCH] drm/i915: fixup l3 parity sysfs access check

[Daniel Vetter]

When l3 parity support for Haswell was enabled in

commit f27b92651d72e863c308ea5dca5615fc98e38ca6
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date:   Tue Jul 24 20:47:32 2012 -0700

    drm/i915: Expand DPF support to Haswell

no one noticed that the patch which introduced this macro

commit e1ef7cc299839e68dae3f1843f62e52acda04538
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date:   Tue Jul 24 20:47:31 2012 -0700

    drm/i915: Macro to determine DPF support

missed one spot. Fix this.

Cc: Ben Widawsky <benjamin.widawsky at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57441
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/i915_sysfs.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 3bf51d5..9462081 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -97,7 +97,7 @@ static struct attribute_group rc6_attr_group = {
 
 static int l3_access_valid(struct drm_device *dev, loff_t offset)
 {
-	if (!IS_IVYBRIDGE(dev))
+	if (!HAS_L3_GPU_CACHE(dev))
 		return -EPERM;
 
 	if (offset % 4 != 0)
-- 
1.7.10.4