[Intel-gfx] [PATCH] Fix intel_detect_pch() to work in xen environment.

[Jesse Barnes]

On Thu, 20 Dec 2012 12:04:11 +0800
"G.R." <firemeteor at users.sourceforge.net> wrote:

> On Wed, Dec 19, 2012 at 2:20 AM, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> >> >
> >> > I'd like to see a comment about this being for Xen in here, and I
> >> > wonder if there are other places where we might have to worry about the
> >> > Xen implementation.  In that case, setting a flag in dev_priv when we
> >> > don't find the PCH where we expect would be a good idea too.
> >> >
> >>
> >> I can add a comment here if the overall idea is acceptable to you.
> >> But there is already a comment mentioning that the ISA bridge check is
> >> for virtualization:
> >>
> >>  404         /*
> >>  405          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
> >>  406          * make graphics device passthrough work easy for VMM, that only
> >>  407          * need to expose ISA bridge to let driver know the real hardware
> >>  408          * underneath. This is a requirement from virtualization team.
> >>  409          */
> >>
> >> > Ack on the general idea though; I'd like us to be able to run under Xen
> >> > without modification.
> >> >
> >>
> >> Stefano may be able to comment if it's feasible to achieve zero
> >> modification in this case.
> >> I believe this has something to do with getting rid of the PIIX3
> >> device provided by qemu.
> >>
> >> But generally I think it's very hard to achieve perfect emulation.
> >> You can't always foresee what assumption a guest driver would make.
> >> Maybe we need some compromise.
> >
> > I meant that I'd like to see any other patches required for Xen get
> > merged, that way people won't have to patch their kernels for i915
> > under Xen.
> 
> Hi Jesse, I think I need to resend the patch with proper comment to
> have it formally accepted.
> Any guide line for formal patch submission? Do I need to start a
> separate thread?

No, just cc Daniel Vetter.

-- 
Jesse Barnes, Intel Open Source Technology Center