[Intel-gfx] [PATCH 1/3] drm/i915: swizzling support for snb/ivb
daniel at ffwll.ch
Wed Feb 1 14:16:19 PST 2012
On Wed, Feb 01, 2012 at 01:35:14PM -0800, Ben Widawsky wrote:
> On 01/31/2012 07:47 AM, Daniel Vetter wrote:
> > We have to do this manually. Somebody had a Great Idea.
> > I've measured speed-ups just a few percent above the noise level
> > (below 5% for the best case), but no slowdows. Chris Wilson measured
> > quite a bit more (10-20% above the usual snb variance) on a more
> > recent and better tuned version of sna, but also recorded a few
> > slow-downs on benchmarks know for uglier amounts of snb-induced
> > variance.
> > v2: Incorporate Ben Widawsky's preliminary review comments and
> > elaborate a bit about the performance impact in the changelog.
> > Acked-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> You didn't address one questions I really cared about, how is it safe to
> ignore channel 3 size? While I'm at it, I wonder what is in these
> registers if you have less than 256MB. If the answer is zero, then your
> check isn't safe enough below.
Hm, I've thought I've answered that in the mail to your review: 3 channel
ddr configurations only exists on i7 chips without a gpu attached.
Furthermore swizzling is only sensible when we have 2 channels anyway.
For the other issue, I suspect 256mb is simply the smallest dimm you can
buy for ddr3 - I don't have the spec for that though, but the smallest
dimm my local supplier sells is 512mb, anyway ;-)
> As an aside, this will potentially break our simulation environment, but
> that's environment fail.
I think we can quirk that by detecting has or something like that ...
Mail: daniel at ffwll.ch
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