[Intel-gfx] [PATCH 1/3] drm/i915: swizzling support for snb/ivb
chris at chris-wilson.co.uk
Wed Feb 1 14:26:08 PST 2012
On Wed, 1 Feb 2012 23:16:19 +0100, Daniel Vetter <daniel at ffwll.ch> wrote:
> On Wed, Feb 01, 2012 at 01:35:14PM -0800, Ben Widawsky wrote:
> > You didn't address one questions I really cared about, how is it safe to
> > ignore channel 3 size? While I'm at it, I wonder what is in these
> > registers if you have less than 256MB. If the answer is zero, then your
> > check isn't safe enough below.
> Hm, I've thought I've answered that in the mail to your review: 3 channel
> ddr configurations only exists on i7 chips without a gpu attached.
> Furthermore swizzling is only sensible when we have 2 channels anyway.
It almost always sensible to leave a comment behind in the code to
address review questions. What may not appear immediately obvious to
another person is unlikely to occur to anyone perusing the code 18+
months later. Didn't future Daniel warn you about that when he travelled
back from December 2012? :)
Chris Wilson, Intel Open Source Technology Centre
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