[Intel-gfx] [PATCH 1/2] drm/i915: specify vertical timings in frame units for interlaced modes (gen4+)

[Daniel Vetter]

On Sun, Jan 15, 2012 at 01:52:11AM +1100, Peter Ross wrote:
> The G35/G45/SandyBridge chipsets expect vertical timings in frame units,
> whereas the DRM subsystem uses field units internally for interlaced modes.
> 
> Signed-off-by: Peter Ross <pross at xvid.org>

On a quick look at the patch it have a confusion about chipset
generations. We generally call g35 i965 to avoid confusion with the gen3
device g33. Also i9xx_crtc_mode_set is only used on pre-ironlake (=gen5)
and hence does not include snb. You might want to fix up
ironlake_crtc_mode_set, too.

When quickly discussing this with Jesse on irc we concluded that this is
fine if it comes with a tested-by (for both patches) attached, preferrably
with quick details on which machines this was tested on.
-Daniel
> ---
>  drivers/gpu/drm/i915/intel_display.c |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2a3f707..ae62f5f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5316,6 +5316,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  		adjusted_mode->crtc_vblank_end -= 1;
>  		adjusted_mode->crtc_vsync_end -= 1;
>  		adjusted_mode->crtc_vsync_start -= 1;
> +		if (INTEL_INFO(dev)->gen >= 4) {
> +			adjusted_mode->crtc_vdisplay *= 2;
> +			adjusted_mode->crtc_vtotal *= 2;
> +			adjusted_mode->crtc_vblank_start *= 2;
> +			adjusted_mode->crtc_vblank_end *= 2;
> +			adjusted_mode->crtc_vsync_end *= 2;
> +			adjusted_mode->crtc_vsync_start *= 2;
> +		}
>  	} else
>  		pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
>  
> -- 
> 1.7.5.4
> 
> -- Peter
> (A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)



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-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48