[Intel-gfx] [PATCH 1/3] drm/i915/dp: Tweak auxch clock divider for PCH

[Daniel Vetter]

On Tue, Jan 17, 2012 at 07:19:35AM -0800, Jesse Barnes wrote:
> On Tue, 26 Jul 2011 15:39:44 -0400
> Adam Jackson <ajax at redhat.com> wrote:
> 
> > Matches the advice in the Sandybridge documentation.
> > 
> > Signed-off-by: Adam Jackson <ajax at redhat.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index dcc7ae6..3ad90f6 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -305,7 +305,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> >  		else
> >  			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
> >  	} else if (HAS_PCH_SPLIT(dev))
> > -		aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
> > +		aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
> >  	else
> >  		aux_clock_divider = intel_hrawclk(dev) / 2;
> 
> I have no problem with this set; matching the docs is nice.  However
> we'll need to get some good test coverage before I feel comfortable.

Ok, Jesse upped these noises of approval into acked-bys on irc. Queued all
3 patches for -next.

Thanks, Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48