[Intel-gfx] [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.
daniel at ffwll.ch
Sat Jan 21 08:36:13 PST 2012
On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote:
> Older specs claimed this was bit 11, but newer specs and the actual
> simulator code say it was bit 12. Regardless, we don't use MI_FLUSH,
> or try to enable it any more.
> Signed-off-by: Eric Anholt <eric at anholt.net>
I'd like to amend this with the following (on this patch instead of the
other, so that ppl actually can find it with git blame):
"Furthermore actually setting bit12 results in gpu hangs both on snb and
ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bit11
must be set, but that doesn't help either. And last but not least,
MI_FLUSH seems to work regardless of the setting of these bits."
Eric, Ben, is that ok?
Mail: daniel at ffwll.ch
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