[Intel-gfx] Valleyview: 3DSTATE_URB_VS Minimum URB Entries

[Cheah, Douglas]

Hello folks,

I am seeing corruption when running spectex from mesa demos which looks like vertex being randomly clipped on Valleyview, however spectex works fine on Ivy Bridge.

After tracing down the codes I realize that the current Mesa driver would program the maximum number or URB entries (512 Valleyview)  whenever possible. This conflict with the 3D pipeline PRM where it states there is a programming restriction if the URB Entry Allocation Size is less than 9 URB entries then total entries should be program to 32. After modifying the codes to meet the restriction I was able to run spectex without corruption on Valleyview, pretty surprise that Ivy Bridge did not have this problem.

Here is the code snippet that I have changed which is at this point a quick hack and not upstream worthy as you can see the macro is not even properly defined in brw_defeines.h. Appreciate if I could get opinions from folks who are more familiar with Mesa and more experience with the graphic core.


static void
gen7_upload_urb(struct brw_context *brw)
{
   struct intel_context *intel = &brw->intel;
   /* Total space for entries is URB size - 16kB for push constants */
   int handle_region_size = (brw->urb.size - 16) * 1024; /* bytes */

   /* CACHE_NEW_VS_PROG */
   brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1);

   int nr_vs_entries = handle_region_size / (brw->urb.vs_size * 64);
   if (nr_vs_entries > brw->urb.max_vs_entries)
      nr_vs_entries = brw->urb.max_vs_entries;

   /* If the number of URB Allocation Size is smaller than 9 512 bit
    * units set the number or URB to Entries to 32
    */
#define GEN7_URB_VS_MIN_ENTRIES 32
   if(brw->urb.vs_size < 9)
        nr_vs_entries = GEN7_URB_VS_MIN_ENTRIES;



Douglas
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