[Intel-gfx] [PATCH 15/21] drm/i915: Timing initialization for eDP on HSW

[Eugeni Dodonov]

From: Shobhit Kumar <shobhit.kumar at intel.com>

v2: simplify horizontal and vertical timings calculations

Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
Signed-off-by: Sateesh Kavuri <sateesh.kavuri at intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 66 +++++++++++++++++++++++-------------
 1 file changed, 42 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9a695ab..0438a10 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4669,6 +4669,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	unsigned int pipe_bpp;
 	bool dither;
 	bool is_cpu_edp = false, is_pch_edp = false;
+	u32 htotal, hblank, hsync, vtotal, vblank, vsync;
 
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
 		if (encoder->base.crtc != crtc)
@@ -4949,7 +4950,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		pipeconf |= PIPECONF_DITHER_EN;
 		pipeconf |= PIPECONF_DITHER_TYPE_SP;
 	}
-	if (is_dp && !is_cpu_edp) {
+	if ((IS_HASWELL(dev) && is_cpu_edp) || (is_dp && !is_cpu_edp)) {
 		intel_dp_set_m_n(crtc, mode, adjusted_mode);
 	} else {
 		/* For non-DP output, clear any trans DP clock recovery setting.*/
@@ -4998,25 +4999,40 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		I915_WRITE(VSYNCSHIFT(pipe), 0);
 	}
 
-	I915_WRITE(HTOTAL(pipe),
-		   (adjusted_mode->crtc_hdisplay - 1) |
-		   ((adjusted_mode->crtc_htotal - 1) << 16));
-	I915_WRITE(HBLANK(pipe),
-		   (adjusted_mode->crtc_hblank_start - 1) |
-		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
-	I915_WRITE(HSYNC(pipe),
-		   (adjusted_mode->crtc_hsync_start - 1) |
-		   ((adjusted_mode->crtc_hsync_end - 1) << 16));
-
-	I915_WRITE(VTOTAL(pipe),
-		   (adjusted_mode->crtc_vdisplay - 1) |
-		   ((adjusted_mode->crtc_vtotal - 1) << 16));
-	I915_WRITE(VBLANK(pipe),
-		   (adjusted_mode->crtc_vblank_start - 1) |
-		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
-	I915_WRITE(VSYNC(pipe),
-		   (adjusted_mode->crtc_vsync_start - 1) |
-		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
+	if (is_cpu_edp && IS_HASWELL(dev)) {
+		htotal = HTOTAL_EDP;
+		hblank = HBLANK_EDP;
+		hsync = HSYNC_EDP;
+		vtotal = VTOTAL_EDP;
+		vblank = VBLANK_EDP;
+		vsync = VSYNC_EDP;
+	} else {
+		htotal = HTOTAL(pipe);
+		hblank = HBLANK(pipe);
+		hsync = HSYNC(pipe);
+		vtotal = VTOTAL(pipe);
+		vblank = VBLANK(pipe);
+		vsync = VSYNC(pipe);
+	}
+	I915_WRITE(htotal,
+		(adjusted_mode->crtc_hdisplay - 1) |
+		((adjusted_mode->crtc_htotal - 1) << 16));
+	I915_WRITE(hblank,
+		(adjusted_mode->crtc_hblank_start - 1) |
+		((adjusted_mode->crtc_hblank_end - 1) << 16));
+	I915_WRITE(hsync,
+		(adjusted_mode->crtc_hsync_start - 1) |
+		((adjusted_mode->crtc_hsync_end - 1) << 16));
+
+	I915_WRITE(vtotal,
+		(adjusted_mode->crtc_vdisplay - 1) |
+		((adjusted_mode->crtc_vtotal - 1) << 16));
+	I915_WRITE(vblank,
+		(adjusted_mode->crtc_vblank_start - 1) |
+		((adjusted_mode->crtc_vblank_end - 1) << 16));
+	I915_WRITE(vsync,
+		(adjusted_mode->crtc_vsync_start - 1) |
+		((adjusted_mode->crtc_vsync_end - 1) << 16));
 
 	/* pipesrc controls the size that is scaled from, which should
 	 * always be the user's requested size.
@@ -5024,10 +5040,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	I915_WRITE(PIPESRC(pipe),
 		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
 
-	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
-	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
-	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
-	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+	if (!is_cpu_edp) {
+		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+	}
 
 	if (is_cpu_edp)
 		ironlake_set_pll_edp(crtc, adjusted_mode->clock);
-- 
1.7.11.1