[Intel-gfx] Broken LVDS output at mode changes

Keith Packard keithp at keithp.com
Thu Mar 29 17:07:05 CEST 2012

<#part sign=pgpmime>
On Thu, 29 Mar 2012 13:44:28 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:

> In conjunction with bits Power Sequence Progress field and Power Cycle
> Delay Active, this bit set to a one indicates that the panel is
> currently powered up or is currently in the power down sequence and it
> is unsafe to change the timing, port, and DPLL registers for the pipe or
> transcoder that is assigned to the panel output.

The theory was that as we don't touch the DPLL and only modify the
scaler, that the panel wouldn't care. I wonder what's confusing this one...

keith.packard at intel.com

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