[Intel-gfx] Broken LVDS output at mode changes
jbarnes at virtuousgeek.org
Fri Mar 30 09:56:48 PDT 2012
On Thu, 29 Mar 2012 13:44:28 +0100
Chris Wilson <chris at chris-wilson.co.uk> wrote:
> On Thu, 29 Mar 2012 14:16:38 +0200, Daniel Vetter <daniel at ffwll.ch> wrote:
> > On Wed, Mar 28, 2012 at 03:29:04PM +0200, Takashi Iwai wrote:
> > > Hi,
> > >
> > > we've encountered a broken LVDS output on some IVY/SNB machines when
> > > the mode is changed (from/to native resolution). When this happens,
> > > the whole laptop panel gets half white and half black. This doesn't
> > > recover until the LVDS is turned off once.
> > >
> > > And, there is no signficant difference between working and non-working
> > > cases in the register dumps. From the software POV, all looks sane.
> > > So, we suspect this is rather specific to some panel hardware.
> > >
> > > However, through debugging, I found that disabling LVDS at mode change
> > > works around the problem. A test patch is attached below.
> > >
> > > My question now is: can this workaround have any serious drawback?
> > > I thought of a longer blank time, but I didn't notice any difference
> > > before and after the patch.
> > >
> > > Or, any other suggestion as a saner fix?
> > No idea, I'm wondering though whether we should just accept some
> > flickering while modesetting unconditionally. Does anyone know what
> > Windows does in this case and at least on my work machine here it looks
> > like Windows just blanks the screen. I haven't checked with reg dumps
> > though how exactly they upscale stuff on lvds.
> > git blame says that Chris Wilson created the original PCH_SPLIT check.
> > Chris, any comments on this?
> It dates back from an earlier commit that presupposes that we can modify
> the panel on the fly and avoid the power-cycling delays.
> PP_STATUS: Panel Power On Status [bit 31]
> In conjunction with bits Power Sequence Progress field and Power Cycle
> Delay Active, this bit set to a one indicates that the panel is
> currently powered up or is currently in the power down sequence and it
> is unsafe to change the timing, port, and DPLL registers for the pipe or
> transcoder that is assigned to the panel output.
> Guess that rules that out.
Yeah but the docs are too conservative there. In many cases it's fine
to modify things while the panel is on, it just requires lots of
testing for the different cases.
On newer chips changing the panel fitting should be ok while the panel
is active, but on older ones we need to shut down the panel first (I
think the split is around Cantiga/Ironlake).
Jesse Barnes, Intel Open Source Technology Center
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