[Intel-gfx] [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

[Jesse Barnes]

On Tue, 23 Oct 2012 12:22:16 +0100
Chris Wilson <chris at chris-wilson.co.uk> wrote:

> On Thu, 18 Oct 2012 13:07:17 -0500, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> > So store into the scratch space of the HWS to make sure the invalidate
> > occurs.
> 
> Whoops, instant hang. Probably doesn't agree with being called FLUSH_SW
> and not FLUSH_DW! ;-)
> 
> > +	/*
> > +	 * Bspec vol 1c.5 - video engine command streamer:
> > +	 * "If ENABLED, all TLBs will be invalidated once the flush
> > +	 * operation is complete. This bit is only valid when the
> > +	 * Post-Sync Operation field is a value of 1h or 3h."
> > +	 */
> >  	if (invalidate & I915_GEM_GPU_DOMAINS)
> > -		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
> > +		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
> > +			MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
> >  	intel_ring_emit(ring, cmd);
> > -	intel_ring_emit(ring, 0);
> > +	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX << 3);
> And here is where the error lies. Perhaps this would be clearer if you
> do:
> 
> #define MI_FLUSH_DW_USE_PPGTT 0
> #define MI_FLUSH_DW_USE_GTT (1<<2)
> 
> #define I915_GEM_HWS_SCRATCH_INDEX 0x30
> #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
> 
> Then:
> 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
> 
> Hangs begone!

Ah cool, was hoping it was something simple.  Damn PPGTT vs GTT always
gets us.

I'll respin with the change.

-- 
Jesse Barnes, Intel Open Source Technology Center