[Intel-gfx] [PATCH] drm/i915: Enable FBC at Haswell.

[Chris Wilson]

On Tue, Apr 16, 2013 at 01:33:44PM -0300, Rodrigo Vivi wrote:
> This patch introduce Frame Buffer Compression (FBC) support for HSW.
> It adds a new function haswell_enable_fbc to avoid getting
> ironlake_enable_fbc messed with many IS_HASWELL checks.
> 
> v2: Fixes from Ville.
>      	*  Fix Plane. FBC is tied to primary plane A in HSW
>     	*  Fix DPFC initial write to avoid let trash on the register.
> 
> v3: Checking for bad plane on intel_update_fbc() as Chris suggested.
> 
> v4: Ville pointed out that according to BSpec FBC_CTL bits 0:3 must be 0.
> 
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>

I'm failing in sanity checking FBC on HSW due to lack of the appropriate
hardware. I still believe we need a cooperative userspace to make best
use of FBC, avoid known limitations and apply required workarounds.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre