[Intel-gfx] [PATCH] drm/i915: Disable WC PTE updates to w/a buggy IOMMU on ILK

[Paul Menzel]

Am Mittwoch, den 13.02.2013, 09:31 +0000 schrieb Chris Wilson:
> Whilst IOMMU is enabled for the Intel GPU on Ironlake, it appears that
> using WC writes to update the PTE on the GPU fail miserably. The result

Either remove using or add an s to fail. ;-)

> looks like the majority of the writes do not land leading to lots of
> screen corruption and a hard system hang.
> 
> v2: s/</<=/ to preserve the current exclusion of Sandybridge
> 
> Reported-by: Nathan Myers <ncm at cantrip.org>
> Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=60391
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: stable at vger.kernel.org
> ---
>  drivers/char/agp/intel-gtt.c |   57 ++++++++++++++++++++++++++----------------
>  1 file changed, 36 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index dbd901e..af85960 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -562,6 +562,40 @@ static void intel_gtt_cleanup(void)
>  	intel_gtt_teardown_scratch_page();
>  }
>  
> +/* Certain Gen5 chipsets require require idling the GPU before

-require

Could you specify »certain« a bit more, please?

> + * unmapping anything from the GTT when VT-d is enabled.
> + */
> +static inline int needs_ilk_vtd_wa(void)
> +{
> +#ifdef CONFIG_INTEL_IOMMU
> +	const unsigned short gpu_devid = intel_private.pcidev->device;
> +
> +	/* Query intel_iommu to see if we need the workaround. Presumably that

• When is a workaround needed?
• I do not understand the second sentence.

> +	 * was loaded first.
> +	 */
> +	if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
> +	     gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
> +	     intel_iommu_gfx_mapped)
> +		return 1;
> +#endif
> +	return 0;
> +}
> +
> +static bool intel_gtt_can_wc(void)
> +{
> +	if (INTEL_GTT_GEN <= 2)
> +		return false;
> +
> +	if (INTEL_GTT_GEN >= 6)
> +		return false;
> +
> +	/* Reports of major corruption with ILK vt'd enabled */

• Full stop at the end?
• s,vt'd,VT-d,?

> +	if (needs_ilk_vtd_wa())
> +		return false;
> +
> +	return true;
> +}
> +
>  static int intel_gtt_init(void)
>  {
>  	u32 gma_addr;
> @@ -591,7 +625,7 @@ static int intel_gtt_init(void)
>  	gtt_map_size = intel_private.base.gtt_total_entries * 4;
>  
>  	intel_private.gtt = NULL;
> -	if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
> +	if (intel_gtt_can_wc())
>  		intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
>  					       gtt_map_size);
>  	if (intel_private.gtt == NULL)
> @@ -1070,25 +1104,6 @@ static void i965_write_entry(dma_addr_t addr,
>  	writel(addr | pte_flags, intel_private.gtt + entry);
>  }
>  
> -/* Certain Gen5 chipsets require require idling the GPU before
> - * unmapping anything from the GTT when VT-d is enabled.
> - */
> -static inline int needs_idle_maps(void)
> -{
> -#ifdef CONFIG_INTEL_IOMMU
> -	const unsigned short gpu_devid = intel_private.pcidev->device;
> -
> -	/* Query intel_iommu to see if we need the workaround. Presumably that
> -	 * was loaded first.

Oh, you just copied that stuff. A follow up patch for the above comments
would be nice then.

> -	 */
> -	if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
> -	     gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
> -	     intel_iommu_gfx_mapped)
> -		return 1;
> -#endif
> -	return 0;
> -}
> -
>  static int i9xx_setup(void)
>  {
>  	u32 reg_addr, gtt_addr;
> @@ -1116,7 +1131,7 @@ static int i9xx_setup(void)
>  		break;
>  	}
>  
> -	if (needs_idle_maps())
> +	if (needs_ilk_vtd_wa())
>  		intel_private.base.do_idle_maps = 1;
>  
>  	intel_i9xx_setup_flush();

With the changes above,

Acked-by: Paul Menzel <paulepanter at users.sourceforge.net>


Thanks,

Paul
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 198 bytes
Desc: This is a digitally signed message part
URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20130213/3a473970/attachment.sig>