[Intel-gfx] [PATCH 02/11] drm/i915: Avoid forcing relocations through the mappable GTT or CPU

[Daniel Vetter]

On Mon, Jan 14, 2013 at 8:21 PM, Imre Deak <imre.deak at intel.com> wrote:
>> +                     drm_clflush_virt_range(vaddr + page_offset, 4);
>> +                     *(uint32_t *)(vaddr + page_offset) = reloc->delta;
>> +                     drm_clflush_virt_range(vaddr + page_offset, 4);
>
> Discussed this already to some degree with Chris, but I still think the
> first cache flush is redundant.

Nope, since it's a partial cacheline write, we need to first flush out
any stale data, then write the dword (which loads the latest data from
memory into a cacheline). Then we need to flush the updated cacheline
out into main memory again. Iirc I've mentioned this somewhere in the
part 4 of my gem intro.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch