[Intel-gfx] [PATCH 5/5] drm/i915: Extract bind object
Ben Widawsky
ben at bwidawsk.net
Mon Jan 21 23:10:36 CET 2013
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
drivers/gpu/drm/i915/i915_drv.h | 11 +++++++++--
drivers/gpu/drm/i915/i915_gem.c | 14 ++++++++------
drivers/gpu/drm/i915/i915_gem_context.c | 4 +++-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 ++++++----
drivers/gpu/drm/i915/i915_gem_gtt.c | 30 ++++++++++++++----------------
5 files changed, 40 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4d7990f..62559b5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -365,6 +365,7 @@ struct intel_device_info {
};
struct i915_gtt;
+enum i915_cache_level;
struct i915_gtt_operations {
int (*gmch_probe)(struct i915_gtt *gtt,
size_t *gtt_total, size_t *stolen);
@@ -372,6 +373,9 @@ struct i915_gtt_operations {
void (*clear_range)(struct i915_gtt *gtt,
unsigned int first_entry,
size_t num_entries);
+ void (*bind_object)(struct i915_gtt *gtt,
+ struct drm_i915_gem_object *obj,
+ enum i915_cache_level cache_level);
#define unbind_object(gtt, obj) \
clear_range(gtt, obj->gtt_space->start >> PAGE_SHIFT, obj->base.size >> PAGE_SHIFT)
@@ -1672,8 +1676,11 @@ void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
void i915_gem_restore_gtt_mappings(struct drm_device *dev);
int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
-void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
- enum i915_cache_level cache_level);
+#define i915_gem_gtt_bind_object(dev_priv, obj, cache_level) \
+ do { \
+ dev_priv->gtt.gtt_ops->bind_object(&dev_priv->gtt, \
+ obj, cache_level); \
+ } while(0)
void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
void i915_gem_init_global_gtt(struct drm_device *dev);
void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 66362b4..97c19d2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3153,8 +3153,10 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
return ret;
}
- if (obj->has_global_gtt_mapping)
- i915_gem_gtt_bind_object(obj, cache_level);
+ if (obj->has_global_gtt_mapping) {
+ i915_gem_gtt_bind_object(dev_priv, obj, cache_level);
+ obj->has_global_gtt_mapping = 1;
+ }
if (obj->has_aliasing_ppgtt_mapping)
i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
obj, cache_level);
@@ -3433,6 +3435,7 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
bool map_and_fenceable,
bool nonblocking)
{
+ struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
int ret;
if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
@@ -3455,8 +3458,6 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
}
if (obj->gtt_space == NULL) {
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
-
ret = i915_gem_object_bind_to_gtt(obj, alignment,
map_and_fenceable,
nonblocking);
@@ -3464,11 +3465,12 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
return ret;
if (!dev_priv->mm.aliasing_ppgtt)
- i915_gem_gtt_bind_object(obj, obj->cache_level);
+ i915_gem_gtt_bind_object(dev_priv, obj,
+ obj->cache_level);
}
if (!obj->has_global_gtt_mapping && map_and_fenceable)
- i915_gem_gtt_bind_object(obj, obj->cache_level);
+ i915_gem_gtt_bind_object(dev_priv, obj, obj->cache_level);
obj->pin_count++;
obj->pin_mappable |= map_and_fenceable;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index a3f06bc..b3304c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -365,6 +365,7 @@ mi_set_context(struct intel_ring_buffer *ring,
static int do_switch(struct i915_hw_context *to)
{
struct intel_ring_buffer *ring = to->ring;
+ struct drm_i915_private *dev_priv = ring->dev->dev_private;
struct drm_i915_gem_object *from_obj = ring->last_context_obj;
u32 hw_flags = 0;
int ret;
@@ -390,7 +391,8 @@ static int do_switch(struct i915_hw_context *to)
}
if (!to->obj->has_global_gtt_mapping)
- i915_gem_gtt_bind_object(to->obj, to->obj->cache_level);
+ i915_gem_gtt_bind_object(dev_priv, to->obj,
+ to->obj->cache_level);
if (!to->is_initialized || is_default_context(to))
hw_flags |= MI_RESTORE_INHIBIT;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 2726910..496f7f2 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -177,6 +177,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
struct drm_i915_gem_relocation_entry *reloc)
{
struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_gem_object *target_obj;
struct drm_i915_gem_object *target_i915_obj;
uint32_t target_offset;
@@ -196,7 +197,8 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
if (unlikely(IS_GEN6(dev) &&
reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
!target_i915_obj->has_global_gtt_mapping)) {
- i915_gem_gtt_bind_object(target_i915_obj,
+ i915_gem_gtt_bind_object(dev_priv,
+ target_i915_obj,
target_i915_obj->cache_level);
}
@@ -267,7 +269,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
*(uint32_t *)(vaddr + page_offset) = reloc->delta;
kunmap_atomic(vaddr);
} else {
- struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t __iomem *reloc_entry;
void __iomem *reloc_page;
@@ -449,7 +450,7 @@ i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
if (entry->flags & EXEC_OBJECT_NEEDS_GTT &&
!obj->has_global_gtt_mapping)
- i915_gem_gtt_bind_object(obj, obj->cache_level);
+ i915_gem_gtt_bind_object(dev_priv, obj, obj->cache_level);
return 0;
}
@@ -990,7 +991,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
* hsw should have this fixed, but let's be paranoid and do it
* unconditionally for now. */
if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
- i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
+ i915_gem_gtt_bind_object(dev_priv, batch_obj,
+ batch_obj->cache_level);
ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5ae1d13..c4e47a0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -403,7 +403,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
i915_gem_clflush_object(obj);
- i915_gem_gtt_bind_object(obj, obj->cache_level);
+ i915_gem_gtt_bind_object(dev_priv, obj, obj->cache_level);
}
i915_gem_chipset_flush(dev);
@@ -428,8 +428,9 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
* within the global GTT as well as accessible by the GPU through the GMADR
* mapped BAR (dev_priv->mm.gtt->gtt).
*/
-static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj,
- enum i915_cache_level level)
+static void gen6_gtt_bind_object(struct i915_gtt *gtt,
+ struct drm_i915_gem_object *obj,
+ enum i915_cache_level level)
{
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -472,21 +473,15 @@ static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj,
POSTING_READ(GFX_FLSH_CNTL_GEN6);
}
-void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
- enum i915_cache_level cache_level)
+void i915_gtt_bind_object(struct i915_gtt *gtt,
+ struct drm_i915_gem_object *obj,
+ enum i915_cache_level cache_level)
{
- struct drm_device *dev = obj->base.dev;
- if (INTEL_INFO(dev)->gen < 6) {
- unsigned int flags = (cache_level == I915_CACHE_NONE) ?
+ unsigned int flags = (cache_level == I915_CACHE_NONE) ?
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
- intel_gtt_insert_sg_entries(obj->pages,
- obj->gtt_space->start >> PAGE_SHIFT,
- flags);
- } else {
- gen6_ggtt_bind_object(obj, cache_level);
- }
-
- obj->has_global_gtt_mapping = 1;
+ intel_gtt_insert_sg_entries(obj->pages,
+ obj->gtt_space->start >> PAGE_SHIFT,
+ flags);
}
void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
@@ -727,6 +722,7 @@ static const struct i915_gtt_operations gen6_gtt_ops = {
.gmch_probe = gen6_gmch_probe,
.gmch_remove = gen6_gmch_remove,
.clear_range = gen6_gtt_clear_range,
+ .bind_object = gen6_gtt_bind_object,
.get_stolen_size = gen6_get_stolen_size,
};
@@ -734,6 +730,7 @@ static const struct i915_gtt_operations gen7_gtt_ops = {
.gmch_probe = gen6_gmch_probe,
.gmch_remove = gen6_gmch_remove,
.clear_range = gen6_gtt_clear_range,
+ .bind_object = gen6_gtt_bind_object,
.get_stolen_size = gen7_get_stolen_size,
};
@@ -773,6 +770,7 @@ static const struct i915_gtt_operations legacy_gtt_ops = {
.gmch_probe = i915_gmch_probe,
.gmch_remove = i915_gmch_remove,
.clear_range = i915_gtt_clear_range,
+ .bind_object = i915_gtt_bind_object,
};
int i915_gem_gtt_init(struct drm_device *dev)
--
1.8.1.1
More information about the Intel-gfx
mailing list