[Intel-gfx] [PATCH 3/8] drm/i915: Read the EDP DPCD and PSR Capability

[Paulo Zanoni]

Hi

2013/1/11 Rodrigo Vivi <rodrigo.vivi at gmail.com>:
> From: Shobhit Kumar <shobhit.kumar at intel.com>
>
> Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
>
> v2: reuse of just created is_edp_psr and put it at right place.
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 12 ++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  include/drm/drm_dp_helper.h      |  1 +
>  3 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1dd89d5..f0224f8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1418,6 +1418,11 @@ static void intel_post_disable_dp(struct intel_encoder *encoder)
>         }
>  }
>
> +static bool is_edp_psr(struct intel_dp *intel_dp)
> +{
> +       return (is_edp(intel_dp) && (intel_dp->psr_dpcd[0] & 0x1));

Bikeshedding:
Since the spec of address 0x70 says "All other values are reserved for
future versions of PSR", maybe we could do something like "return
(is_edp(intel_dp) && !(intel_dp->psr_dpcd[0] == 0)" ?

> +}
> +
>  static void intel_enable_dp(struct intel_encoder *encoder)
>  {
>         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> @@ -2094,6 +2099,13 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
>                 return false; /* DPCD not present */
>
> +       /* Check if the panel supports PSR */
> +       memset(intel_dp->psr_dpcd, 0, EDP_PSR_RECEIVER_CAP_SIZE);
> +       intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
> +                                      intel_dp->psr_dpcd,
> +                                      sizeof(intel_dp->psr_dpcd));
> +       if (is_edp_psr(intel_dp))
> +               DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
>         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
>               DP_DWN_STRM_PORT_PRESENT))
>                 return true; /* native DP sink */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9799fe9..82a85ad 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -360,6 +360,7 @@ struct intel_dp {
>         uint8_t link_bw;
>         uint8_t lane_count;
>         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
> +       uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>         struct i2c_adapter adapter;
>         struct i2c_algo_dp_aux_data algo;
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index c09d367..32eeb92 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -335,6 +335,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
>                                           int lane);
>
>  #define DP_RECEIVER_CAP_SIZE   0xf
> +#define EDP_PSR_RECEIVER_CAP_SIZE      2
>  void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
>  void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
>
> --
> 1.7.11.7
>
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-- 
Paulo Zanoni