[Intel-gfx] [PATCH 29/33] drm/i915: VGA registers need an offset on VLV

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c149426..75b46c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -133,25 +133,25 @@
 
 /* VGA stuff */
 
-#define VGA_ST01_MDA 0x3ba
-#define VGA_ST01_CGA 0x3da
+#define VGA_ST01_MDA (dev_priv->info->display_mmio_offset + 0x3ba)
+#define VGA_ST01_CGA (dev_priv->info->display_mmio_offset + 0x3da)
 
-#define VGA_MSR_WRITE 0x3c2
-#define VGA_MSR_READ 0x3cc
+#define VGA_MSR_WRITE (dev_priv->info->display_mmio_offset + 0x3c2)
+#define VGA_MSR_READ (dev_priv->info->display_mmio_offset + 0x3cc)
 #define   VGA_MSR_MEM_EN (1<<1)
 #define   VGA_MSR_CGA_MODE (1<<0)
 
-#define VGA_SR_INDEX 0x3c4
+#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4)
 #define SR01			1
-#define VGA_SR_DATA 0x3c5
+#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5)
 
-#define VGA_AR_INDEX 0x3c0
+#define VGA_AR_INDEX (dev_priv->info->display_mmio_offset + 0x3c0)
 #define   VGA_AR_VID_EN (1<<5)
-#define VGA_AR_DATA_WRITE 0x3c0
-#define VGA_AR_DATA_READ 0x3c1
+#define VGA_AR_DATA_WRITE (dev_priv->info->display_mmio_offset + 0x3c0)
+#define VGA_AR_DATA_READ (dev_priv->info->display_mmio_offset + 0x3c1)
 
-#define VGA_GR_INDEX 0x3ce
-#define VGA_GR_DATA 0x3cf
+#define VGA_GR_INDEX (dev_priv->info->display_mmio_offset + 0x3ce)
+#define VGA_GR_DATA (dev_priv->info->display_mmio_offset + 0x3cf)
 /* GR05 */
 #define   VGA_GR_MEM_READ_MODE_SHIFT 3
 #define     VGA_GR_MEM_READ_MODE_PLANE 1
@@ -163,15 +163,15 @@
 #define   VGA_GR_MEM_B0000_B7FFF 2
 #define   VGA_GR_MEM_B0000_BFFFF 3
 
-#define VGA_DACMASK 0x3c6
-#define VGA_DACRX 0x3c7
-#define VGA_DACWX 0x3c8
-#define VGA_DACDATA 0x3c9
+#define VGA_DACMASK (dev_priv->info->display_mmio_offset + 0x3c6)
+#define VGA_DACRX (dev_priv->info->display_mmio_offset + 0x3c7)
+#define VGA_DACWX (dev_priv->info->display_mmio_offset + 0x3c8)
+#define VGA_DACDATA (dev_priv->info->display_mmio_offset + 0x3c9)
 
-#define VGA_CR_INDEX_MDA 0x3b4
-#define VGA_CR_DATA_MDA 0x3b5
-#define VGA_CR_INDEX_CGA 0x3d4
-#define VGA_CR_DATA_CGA 0x3d5
+#define VGA_CR_INDEX_MDA (dev_priv->info->display_mmio_offset + 0x3b4)
+#define VGA_CR_DATA_MDA (dev_priv->info->display_mmio_offset + 0x3b5)
+#define VGA_CR_INDEX_CGA (dev_priv->info->display_mmio_offset + 0x3d4)
+#define VGA_CR_DATA_CGA (dev_priv->info->display_mmio_offset + 0x3d5)
 
 /*
  * Memory interface instructions used by the kernel
-- 
1.7.12.4