[Intel-gfx] [PATCH 33/33] drm/i915: Kill VLV specific interrupts registers
ville.syrjala at linux.intel.com
ville.syrjala at linux.intel.com
Thu Jan 24 14:29:58 CET 2013
From: Ville Syrjälä <ville.syrjala at linux.intel.com>
Apart from VLV_IIR_RW all the VLV interrupt registers are the
same as on pre-PCH platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++---
drivers/gpu/drm/i915/i915_irq.c | 44 ++++++++++++++++++-------------------
drivers/gpu/drm/i915/i915_reg.h | 12 ++++------
3 files changed, 29 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 18971f5..76c5b2f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -430,13 +430,13 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
if (IS_VALLEYVIEW(dev)) {
seq_printf(m, "Display IER:\t%08x\n",
- I915_READ(VLV_IER));
+ I915_READ(IER));
seq_printf(m, "Display IIR:\t%08x\n",
- I915_READ(VLV_IIR));
+ I915_READ(IIR));
seq_printf(m, "Display IIR_RW:\t%08x\n",
I915_READ(VLV_IIR_RW));
seq_printf(m, "Display IMR:\t%08x\n",
- I915_READ(VLV_IMR));
+ I915_READ(IMR));
for_each_pipe(pipe)
seq_printf(m, "Pipe %c stat:\t%08x\n",
pipe_name(pipe),
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9a9dda1..48c23af 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -552,7 +552,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
atomic_inc(&dev_priv->irq_received);
while (true) {
- iir = I915_READ(VLV_IIR);
+ iir = I915_READ(IIR);
gt_iir = I915_READ(GTIIR);
pm_iir = I915_READ(GEN6_PMIIR);
@@ -612,7 +612,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
I915_WRITE(GTIIR, gt_iir);
I915_WRITE(GEN6_PMIIR, pm_iir);
- I915_WRITE(VLV_IIR, iir);
+ I915_WRITE(IIR, iir);
}
out:
@@ -1317,7 +1317,7 @@ static void i915_capture_error_state(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev))
error->ier = I915_READ(DEIER) | I915_READ(GTIER);
else if (IS_VALLEYVIEW(dev))
- error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
+ error->ier = I915_READ(GTIER) | I915_READ(IER);
else if (IS_GEN2(dev))
error->ier = I915_READ16(IER);
else
@@ -1659,12 +1659,12 @@ static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
return -EINVAL;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- imr = I915_READ(VLV_IMR);
+ imr = I915_READ(IMR);
if (pipe == 0)
imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
else
imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
- I915_WRITE(VLV_IMR, imr);
+ I915_WRITE(IMR, imr);
i915_enable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -1721,12 +1721,12 @@ static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
i915_disable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
- imr = I915_READ(VLV_IMR);
+ imr = I915_READ(IMR);
if (pipe == 0)
imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
else
imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
- I915_WRITE(VLV_IMR, imr);
+ I915_WRITE(IMR, imr);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
@@ -1892,7 +1892,7 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
atomic_set(&dev_priv->irq_received, 0);
/* VLV magic */
- I915_WRITE(VLV_IMR, 0);
+ I915_WRITE(IMR, 0);
I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
@@ -1910,10 +1910,10 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
for_each_pipe(pipe)
I915_WRITE(PIPESTAT(pipe), 0xffff);
- I915_WRITE(VLV_IIR, 0xffffffff);
- I915_WRITE(VLV_IMR, 0xffffffff);
- I915_WRITE(VLV_IER, 0x0);
- POSTING_READ(VLV_IER);
+ I915_WRITE(IIR, 0xffffffff);
+ I915_WRITE(IMR, 0xffffffff);
+ I915_WRITE(IER, 0x0);
+ POSTING_READ(IER);
}
/*
@@ -2097,19 +2097,19 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_EN, 0);
POSTING_READ(PORT_HOTPLUG_EN);
- I915_WRITE(VLV_IMR, dev_priv->irq_mask);
- I915_WRITE(VLV_IER, enable_mask);
- I915_WRITE(VLV_IIR, 0xffffffff);
+ I915_WRITE(IMR, dev_priv->irq_mask);
+ I915_WRITE(IER, enable_mask);
+ I915_WRITE(IIR, 0xffffffff);
I915_WRITE(PIPESTAT(0), 0xffff);
I915_WRITE(PIPESTAT(1), 0xffff);
- POSTING_READ(VLV_IER);
+ POSTING_READ(IER);
i915_enable_pipestat(dev_priv, 0, pipestat_enable);
i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
i915_enable_pipestat(dev_priv, 1, pipestat_enable);
- I915_WRITE(VLV_IIR, 0xffffffff);
- I915_WRITE(VLV_IIR, 0xffffffff);
+ I915_WRITE(IIR, 0xffffffff);
+ I915_WRITE(IIR, 0xffffffff);
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
@@ -2170,10 +2170,10 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
for_each_pipe(pipe)
I915_WRITE(PIPESTAT(pipe), 0xffff);
- I915_WRITE(VLV_IIR, 0xffffffff);
- I915_WRITE(VLV_IMR, 0xffffffff);
- I915_WRITE(VLV_IER, 0x0);
- POSTING_READ(VLV_IER);
+ I915_WRITE(IIR, 0xffffffff);
+ I915_WRITE(IMR, 0xffffffff);
+ I915_WRITE(IER, 0x0);
+ POSTING_READ(IER);
}
static void ironlake_irq_uninstall(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75b46c8..092066f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -555,17 +555,13 @@
#define VLV_DISPLAY_BASE 0x180000
#define SCPD0 0x0209c /* 915+ only */
-#define IER 0x020a0
-#define IIR 0x020a4
-#define IMR 0x020a8
-#define ISR 0x020ac
+#define IER (dev_priv->info->display_mmio_offset + 0x20a0)
+#define IIR (dev_priv->info->display_mmio_offset + 0x20a4)
+#define IMR (dev_priv->info->display_mmio_offset + 0x20a8)
+#define ISR (dev_priv->info->display_mmio_offset + 0x20ac)
#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
#define GCFG_DIS (1<<8)
#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
-#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
-#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
-#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
-#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
--
1.7.12.4
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