[Intel-gfx] [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV

[Daniel Vetter]

On Fri, Jan 25, 2013 at 12:51:15PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 24, 2013 at 11:41:53PM +0100, Daniel Vetter wrote:
> > On Thu, Jan 24, 2013 at 03:29:50PM +0200, ville.syrjala at linux.intel.com wrote:
> > >  #define  DSTATE_GFX_RESET_I830			(1<<6)
> > >  #define  DSTATE_PLL_D3_OFF			(1<<3)
> > >  #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
> > >  #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
> > > -#define DSPCLK_GATE_D		0x6200
> > > +#define DSPCLK_GATE_D		(dev_priv->info->display_mmio_offset + 0x6200)
> > 
> > This one here seems to be only used up to gen4 ...
> 
> DSPCLK_GATE_D is used in intel_i2c_quirk_set(). OTOH gma500 has the
> same code commented out, so it may be that we can skip it too. Anyone
> have more details on this quirk?

Afaict that quirk is for pnv only.

> gma500 also seems to use DSPCLK_GATE_D to disable clock gating for
> some DP stuff on CDV. Considering the lineage we need to find out
> if that's something that affects VLV as well.

I guess we could add it once we need it in a vlv clock gating functions.
Generally we tend to only add clock gating defines when we need them,
since there are soooooo many.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch