[Intel-gfx] [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV

[Ville Syrjälä]

On Fri, Jan 25, 2013 at 06:20:53PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 25, 2013 at 05:06:51PM +0100, Daniel Vetter wrote:
> > On Fri, Jan 25, 2013 at 12:51:15PM +0200, Ville Syrjälä wrote:
> > > On Thu, Jan 24, 2013 at 11:41:53PM +0100, Daniel Vetter wrote:
> > > > On Thu, Jan 24, 2013 at 03:29:50PM +0200, ville.syrjala at linux.intel.com wrote:
> > > > >  #define  DSTATE_GFX_RESET_I830			(1<<6)
> > > > >  #define  DSTATE_PLL_D3_OFF			(1<<3)
> > > > >  #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
> > > > >  #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
> > > > > -#define DSPCLK_GATE_D		0x6200
> > > > > +#define DSPCLK_GATE_D		(dev_priv->info->display_mmio_offset + 0x6200)
> > > > 
> > > > This one here seems to be only used up to gen4 ...
> > > 
> > > DSPCLK_GATE_D is used in intel_i2c_quirk_set(). OTOH gma500 has the
> > > same code commented out, so it may be that we can skip it too. Anyone
> > > have more details on this quirk?
> > 
> > Afaict that quirk is for pnv only.
> 
> So, should we just kill it for other HW? At least it needs to be killed
> for VLV if we don't merge this hunk.

Ah, it already is disabled for everything else. Great, less work for
me.

-- 
Ville Syrjälä
Intel OTC