[Intel-gfx] [PATCH 02/10] drm/i915: We implement WaFbcAsynchFlipDisableFbcQueue on ilk and snb

[Paulo Zanoni]

2013/6/7 Damien Lespiau <damien.lespiau at intel.com>:
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 57e99b1..eb3c2c4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4420,6 +4420,8 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
>          * The bit 22 of 0x42000
>          * The bit 22 of 0x42004
>          * The bit 7,8,9 of 0x42020.
> +        *
> +        * WaFbcAsynchFlipDisableFbcQueue:ilk
>          */
>         if (IS_IRONLAKE_M(dev)) {
>                 I915_WRITE(ILK_DISPLAY_CHICKEN1,

Inside the IS_IRONLAKE_M check we set 2 chicken bits. Does the WA
apply to both? It seem it only applies to ILK_DISPLAY_CHICKEN1, so my
suggestion would be to move the comment down to inside the "if"
statement, just above the ILK_DISPLAY_CHICKEN1 line. With the WA
comment above the "if" statement it seems the WA applies to both
i915_writes. Anyway, Reviewed-by: Paulo Zanoni
<paulo.r.zanoni at intel.com>

> @@ -4557,6 +4559,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>          * The bit5 and bit7 of 0x42020
>          * The bit14 of 0x70180
>          * The bit14 of 0x71180
> +        *
> +        * WaFbcAsynchFlipDisableFbcQueue:snb
>          */
>         I915_WRITE(ILK_DISPLAY_CHICKEN1,
>                    I915_READ(ILK_DISPLAY_CHICKEN1) |
> --
> 1.8.1.4
>
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-- 
Paulo Zanoni