[Intel-gfx] [PATCH 6/6] drm/i915: HSW FBC WaFbcDisableDpfcClockGating

[Paulo Zanoni]

Hi

I just tested this series on Haswell, on top of dinq + my watermark
patches. I applied these 6 patches + "Revert "drm/i915: Calculate
correct stolen size for GEN7+"".

Without FBC I was getting around 2.5% PC7 residency with 1920x1080.
Now with a full-screen black-background terminal I get 66% residency
on PC7. With a maximized firefox displaying my gmail inbox on xfce4 I
get around 55% PC7 residency. With all minimized applications and
Xubuntu's default desktop background I get around 60% PC7 residency.
With full-screen firefox displaying the results for the google image
search for the word "wallpaper" I get around 47% PC7 residency.

But remember: this also requires the watermark patches I submitted :)

I've been testing this for only a few minutes, but I haven't seen any
corruption problems and I plan to keep these patches applied, so
regressions will be reported. I'm not sure if that matters, but I'm
using SNA on an old version of the DDX driver.
For the series:
Tested-by: Paulo Zanoni <paulo.r.zanoni at intel.com> (briefly tested on Haswell)

2013/5/6 Rodrigo Vivi <rodrigo.vivi at gmail.com>:
> Display register 46500h bit 23 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
>
> v2: Ville suggested to enable it back when disabling fbc to avoid wasting
>     power.
>
> v3: RMW to preserve other bits (by Ville)
> v4: Fix from Ville: sed &/| at RMW
>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
>  2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a17480e..40a59e5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -986,6 +986,9 @@
>                                              _HSW_PIPE_SLICE_CHICKEN_1_A, + \
>                                              _HSW_PIPE_SLICE_CHICKEN_1_B)
>
> +#define HSW_CLKGATE_DISABLE_PART_1     0x46500
> +#define   HSW_DPFC_GATING_DISABLE      (1<<23)
> +
>  /*
>   * GPIO regs
>   */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f074c0c..9b5a38c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -248,6 +248,12 @@ static void ironlake_disable_fbc(struct drm_device *dev)
>                                    I915_READ(ILK_DSPCLK_GATE_D) |
>                                    ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
>
> +               if(IS_HASWELL(dev))
> +                       /* WaFbcDisableDpfcClockGating */
> +                       I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
> +                                  I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
> +                                  ~HSW_DPFC_GATING_DISABLE);
> +
>                 DRM_DEBUG_KMS("disabled FBC\n");
>         }
>  }
> @@ -285,6 +291,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>                 /* WaFbcAsynchFlipDisableFbcQueue */
>                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
>                            HSW_BYPASS_FBC_QUEUE);
> +               /* WaFbcDisableDpfcClockGating */
> +               I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
> +                          I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
> +                          HSW_DPFC_GATING_DISABLE);
>         }
>
>         I915_WRITE(SNB_DPFC_CTL_SA,
> --
> 1.7.11.7
>
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-- 
Paulo Zanoni