[Intel-gfx] [PATCH] drm/i915/bdw: PIPE_[BC] I[ME]R moved to powerwell

[Daniel Vetter]

On Fri, Nov 08, 2013 at 02:29:46PM -0800, Ben Widawsky wrote:
> The pipe B and pipe C interrupt mask and enable registers are now part
> of the pipe, so disabling the pipe power wells will lost the contests of
> the registers.
> 
> Art totally debugged this one!
> 
> Cc: Art Runyan <arthur.j.runyan at intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0a07d7c..d68cec4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5701,6 +5701,18 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable)
>  				      HSW_PWR_WELL_STATE_ENABLED), 20))
>  				DRM_ERROR("Timeout enabling power well\n");
>  		}
> +
> +		if (IS_BROADWELL(dev)) {
> +			I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
> +				   dev_priv->de_irq_mask[PIPE_B]);
> +			I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
> +				   ~dev_priv->de_irq_mask[PIPE_B] | GEN8_PIPE_VBLANK);
> +			I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
> +				   dev_priv->de_irq_mask[PIPE_C]);
> +			I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
> +				   ~dev_priv->de_irq_mask[PIPE_C] | GEN8_PIPE_VBLANK);
> +			POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));

This needs to be protected by the dev_priv->irq_lock in case we see
concurrent changes from elseplace. It shouldn't be possible since if a
pipe is off we shouldn't ever ask for vblank or pageflip interrupts. But
given the mess that is drm_irq.c I wouldn't trust that.

Hm, actually if we'd shovel this into ->crtc_enable hook before we update
crtc->active we'd see this guarantee a bit more clearly. But imo ok to do
here, too.
-Daniel

> +		}
>  	} else {
>  		if (enable_requested) {
>  			unsigned long irqflags;
> -- 
> 1.8.4.2
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch