[Intel-gfx] [PATCH 2/4] drm/i915: Use FLISDSI interface for band gap reset

[Jani Nikula]

Hmm, I don't think I have the spec for this one. So did not check the
values, but overall the code looks good.

With the above limitation,
Reviewed-by: Jani Nikula <jani.nikula at intel.com>


On Mon, 21 Oct 2013, Shobhit Kumar <shobhit.kumar at intel.com> wrote:
> Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |    2 ++
>  drivers/gpu/drm/i915/i915_reg.h       |    1 +
>  drivers/gpu/drm/i915/intel_dsi.c      |   47 ++++++---------------------------
>  drivers/gpu/drm/i915/intel_sideband.c |   14 ++++++++++
>  4 files changed, 25 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index faf4dc1..1c42bb4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2334,6 +2334,8 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
>  		   enum intel_sbi_destination destination);
>  void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
>  		     enum intel_sbi_destination destination);
> +u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> +void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  
>  int vlv_gpu_freq(int ddr_freq, int val);
>  int vlv_freq_opcode(int ddr_freq, int val);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 852d3c4..172f490 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -355,6 +355,7 @@
>  #define   IOSF_PORT_CCK				0x14
>  #define   IOSF_PORT_CCU				0xA9
>  #define   IOSF_PORT_GPS_CORE			0x48
> +#define   IOSF_PORT_FLISDSI			0x1B
>  #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
>  #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 34e19b7..5a9dbfd 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -37,49 +37,18 @@
>  static const struct intel_dsi_device intel_dsi_devices[] = {
>  };
>  
> -
> -static void vlv_cck_modify(struct drm_i915_private *dev_priv, u32 reg, u32 val,
> -			   u32 mask)
> -{
> -	u32 tmp = vlv_cck_read(dev_priv, reg);
> -	tmp &= ~mask;
> -	tmp |= val;
> -	vlv_cck_write(dev_priv, reg, tmp);
> -}
> -
> -static void band_gap_wa(struct drm_i915_private *dev_priv)
> +static void band_gap_reset(struct drm_i915_private *dev_priv)
>  {
>  	mutex_lock(&dev_priv->dpio_lock);
>  
> -	/* Enable bandgap fix in GOP driver */
> -	vlv_cck_modify(dev_priv, 0x6D, 0x00010000, 0x00030000);
> -	msleep(20);
> -	vlv_cck_modify(dev_priv, 0x6E, 0x00010000, 0x00030000);
> -	msleep(20);
> -	vlv_cck_modify(dev_priv, 0x6F, 0x00010000, 0x00030000);
> -	msleep(20);
> -	vlv_cck_modify(dev_priv, 0x00, 0x00008000, 0x00008000);
> -	msleep(20);
> -	vlv_cck_modify(dev_priv, 0x00, 0x00000000, 0x00008000);
> -	msleep(20);
> -
> -	/* Turn Display Trunk on */
> -	vlv_cck_modify(dev_priv, 0x6B, 0x00020000, 0x00030000);
> -	msleep(20);
> -
> -	vlv_cck_modify(dev_priv, 0x6C, 0x00020000, 0x00030000);
> -	msleep(20);
> -
> -	vlv_cck_modify(dev_priv, 0x6D, 0x00020000, 0x00030000);
> -	msleep(20);
> -	vlv_cck_modify(dev_priv, 0x6E, 0x00020000, 0x00030000);
> -	msleep(20);
> -	vlv_cck_modify(dev_priv, 0x6F, 0x00020000, 0x00030000);
> +	vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
> +	vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
> +	vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
> +	udelay(150);
> +	vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
> +	vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
>  
>  	mutex_unlock(&dev_priv->dpio_lock);
> -
> -	/* Need huge delay, otherwise clock is not stable */
> -	msleep(100);
>  }
>  
>  static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
> @@ -363,7 +332,7 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
>  	vlv_enable_dsi_pll(intel_encoder);
>  
>  	/* XXX: Location of the call */
> -	band_gap_wa(dev_priv);
> +	band_gap_reset(dev_priv);
>  
>  	/* escape clock divider, 20MHz, shared for A and C. device ready must be
>  	 * off when doing this! txclkesc? */
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index acd1cfe..e3f5210 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -239,3 +239,17 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
>  		return;
>  	}
>  }
> +
> +u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
> +{
> +	u32 val = 0;
> +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
> +					DPIO_OPCODE_REG_READ, reg, &val);
> +	return val;
> +}
> +
> +void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> +{
> +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
> +					DPIO_OPCODE_REG_WRITE, reg, &val);
> +}
> -- 
> 1.7.9.5
>

-- 
Jani Nikula, Intel Open Source Technology Center